164 lines
11 KiB
Plaintext
164 lines
11 KiB
Plaintext
Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
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| Date : Wed Apr 22 08:02:12 2015
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| Host : jrpotter running 64-bit major release (build 9200)
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| Command : report_clock_utilization -file top_clock_utilization_placed.rpt
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| Design : top
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| Device : xc7a100t
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------------------------------------------------------------------------------------
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Clock Utilization Report
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Table of Contents
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-----------------
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1. Clock Primitive Utilization
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2. Details of Global Clocks
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3. Details of Regional Clocks
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4. Details of Multi-Regional Clocks
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5. Details of I/O Clocks
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6. Details of Local Clocks
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7. Clock Regions : Key Resource Utilization
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8. Net wise resources used in clock region X1Y1
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9. Net wise resources used in clock region X1Y2
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1. Clock Primitive Utilization
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------------------------------
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+-------+------+-----------+-----------+
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| Type | Used | Available | Num Fixed |
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+-------+------+-----------+-----------+
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| BUFG | 3 | 32 | 0 |
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| BUFH | 0 | 96 | 0 |
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| BUFIO | 0 | 24 | 0 |
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| MMCM | 1 | 6 | 0 |
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| PLL | 0 | 6 | 0 |
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| BUFR | 0 | 24 | 0 |
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| BUFMR | 0 | 12 | 0 |
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+-------+------+-----------+-----------+
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2. Details of Global Clocks
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---------------------------
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+-------+----------------+---------------+--------------+-------+---------------+-----------+
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| | | | Num Loads | | | |
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+-------+----------------+---------------+------+-------+-------+---------------+-----------+
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| Index | BUFG Cell | Net Name | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) |
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+-------+----------------+---------------+------+-------+-------+---------------+-----------+
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| 1 | clkdv/bufclkfb | clkdv/clkfbin | 1 | 1 | no | 1.711 | 0.086 |
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| 2 | clkdv/buf100 | clkdv/clk100 | 26 | 8 | no | 1.881 | 0.153 |
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| 3 | clkdv/buf12 | clkdv/clk12 | 570 | 144 | no | 1.887 | 0.257 |
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+-------+----------------+---------------+------+-------+-------+---------------+-----------+
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+-------+------------+----------------+--------------+-------+---------------+-----------+
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| | | | Num Loads | | | |
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+-------+------------+----------------+------+-------+-------+---------------+-----------+
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| Index | MMCM Cell | Net Name | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) |
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+-------+------------+----------------+------+-------+-------+---------------+-----------+
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| 1 | clkdv/mmcm | clkdv/clkfbout | 1 | 1 | no | 1.719 | 0.086 |
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| 2 | clkdv/mmcm | clkdv/clkout3 | 1 | 1 | no | 1.719 | 0.086 |
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| 3 | clkdv/mmcm | clkdv/clkout0 | 4 | 2 | no | 1.719 | 1.593 |
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+-------+------------+----------------+------+-------+-------+---------------+-----------+
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3. Details of Regional Clocks
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-----------------------------
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4. Details of Multi-Regional Clocks
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-----------------------------------
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5. Details of I/O Clocks
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------------------------
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6. Details of Local Clocks
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--------------------------
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7. Clock Regions : Key Resource Utilization
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-------------------------------------------
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+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
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| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E1 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 20800 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12000 | 0 | 2200 | 0 | 40 | 0 | 20 | 0 | 40 |
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| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 16000 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 135 | 15200 | 438 | 2600 | 0 | 60 | 0 | 30 | 0 | 40 |
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| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 16000 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y2 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 26 | 15200 | 0 | 2600 | 0 | 60 | 0 | 30 | 0 | 40 |
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| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 20800 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 |
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| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 10800 | 0 | 2000 | 0 | 30 | 0 | 15 | 0 | 40 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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* RAMB36 site can be used as two RAMB18/FIFO18 sites
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8. Net wise resources used in clock region X1Y1
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-----------------------------------------------
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+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
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| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name |
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+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
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| BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | clkdv/clk100 |
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| BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 109 | 438 | 0 | clkdv/clk12 |
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+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
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9. Net wise resources used in clock region X1Y2
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-----------------------------------------------
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+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
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| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name |
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+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
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| BUFG | --- | no | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clkdv/clkfbin |
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| BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 0 | 0 | clkdv/clk12 |
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+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+
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# Location of BUFG Primitives
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set_property LOC BUFGCTRL_X0Y17 [get_cells clkdv/buf100]
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set_property LOC BUFGCTRL_X0Y16 [get_cells clkdv/buf12]
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set_property LOC BUFGCTRL_X0Y18 [get_cells clkdv/bufclkfb]
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# Location of IO Clock Primitives
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# Location of MMCM Clock Primitives
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set_property LOC MMCME2_ADV_X1Y2 [get_cells clkdv/mmcm]
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# Location of BUFH Clock Primitives
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# Location of BUFR Clock Primitives
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# Location of BUFMR Clock Primitives
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# Location of PLL Clock Primitives
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# Location of IO Primitives which is load of clock spine
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# Location of clock ports
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set_property LOC IOB_X1Y126 [get_ports clk]
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# Clock net "clkdv/clk100" driven by instance "clkdv/buf100" located at site "BUFGCTRL_X0Y17"
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#startgroup
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create_pblock CLKAG_clkdv/clk100
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add_cells_to_pblock [get_pblocks CLKAG_clkdv/clk100] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clk100"}]]]
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resize_pblock [get_pblocks CLKAG_clkdv/clk100] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}
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#endgroup
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# Clock net "clkdv/clk12" driven by instance "clkdv/buf12" located at site "BUFGCTRL_X0Y16"
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#startgroup
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create_pblock CLKAG_clkdv/clk12
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add_cells_to_pblock [get_pblocks CLKAG_clkdv/clk12] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clk12"}]]]
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resize_pblock [get_pblocks CLKAG_clkdv/clk12] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}
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#endgroup
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# Clock net "clkdv/clkout0" driven by instance "clkdv/mmcm" located at site "MMCME2_ADV_X1Y2"
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#startgroup
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create_pblock CLKAG_clkdv/clkout0
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add_cells_to_pblock [get_pblocks CLKAG_clkdv/clkout0] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=clkdv/buf100} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clkout0"}]]]
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resize_pblock [get_pblocks CLKAG_clkdv/clkout0] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
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#endgroup
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