Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 | Date : Wed Apr 22 08:02:12 2015 | Host : jrpotter running 64-bit major release (build 9200) | Command : report_clock_utilization -file top_clock_utilization_placed.rpt | Design : top | Device : xc7a100t ------------------------------------------------------------------------------------ Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Details of Global Clocks 3. Details of Regional Clocks 4. Details of Multi-Regional Clocks 5. Details of I/O Clocks 6. Details of Local Clocks 7. Clock Regions : Key Resource Utilization 8. Net wise resources used in clock region X1Y1 9. Net wise resources used in clock region X1Y2 1. Clock Primitive Utilization ------------------------------ +-------+------+-----------+-----------+ | Type | Used | Available | Num Fixed | +-------+------+-----------+-----------+ | BUFG | 3 | 32 | 0 | | BUFH | 0 | 96 | 0 | | BUFIO | 0 | 24 | 0 | | MMCM | 1 | 6 | 0 | | PLL | 0 | 6 | 0 | | BUFR | 0 | 24 | 0 | | BUFMR | 0 | 12 | 0 | +-------+------+-----------+-----------+ 2. Details of Global Clocks --------------------------- +-------+----------------+---------------+--------------+-------+---------------+-----------+ | | | | Num Loads | | | | +-------+----------------+---------------+------+-------+-------+---------------+-----------+ | Index | BUFG Cell | Net Name | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) | +-------+----------------+---------------+------+-------+-------+---------------+-----------+ | 1 | clkdv/bufclkfb | clkdv/clkfbin | 1 | 1 | no | 1.711 | 0.086 | | 2 | clkdv/buf100 | clkdv/clk100 | 26 | 8 | no | 1.881 | 0.153 | | 3 | clkdv/buf12 | clkdv/clk12 | 570 | 144 | no | 1.887 | 0.257 | +-------+----------------+---------------+------+-------+-------+---------------+-----------+ +-------+------------+----------------+--------------+-------+---------------+-----------+ | | | | Num Loads | | | | +-------+------------+----------------+------+-------+-------+---------------+-----------+ | Index | MMCM Cell | Net Name | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) | +-------+------------+----------------+------+-------+-------+---------------+-----------+ | 1 | clkdv/mmcm | clkdv/clkfbout | 1 | 1 | no | 1.719 | 0.086 | | 2 | clkdv/mmcm | clkdv/clkout3 | 1 | 1 | no | 1.719 | 0.086 | | 3 | clkdv/mmcm | clkdv/clkout0 | 4 | 2 | no | 1.719 | 1.593 | +-------+------------+----------------+------+-------+-------+---------------+-----------+ 3. Details of Regional Clocks ----------------------------- 4. Details of Multi-Regional Clocks ----------------------------------- 5. Details of I/O Clocks ------------------------ 6. Details of Local Clocks -------------------------- 7. Clock Regions : Key Resource Utilization ------------------------------------------- +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E1 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 20800 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12000 | 0 | 2200 | 0 | 40 | 0 | 20 | 0 | 40 | | X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 16000 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 135 | 15200 | 438 | 2600 | 0 | 60 | 0 | 30 | 0 | 40 | | X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 16000 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y2 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 26 | 15200 | 0 | 2600 | 0 | 60 | 0 | 30 | 0 | 40 | | X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 20800 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 10800 | 0 | 2000 | 0 | 30 | 0 | 15 | 0 | 40 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * RAMB36 site can be used as two RAMB18/FIFO18 sites 8. Net wise resources used in clock region X1Y1 ----------------------------------------------- +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ | Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name | +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ | BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | clkdv/clk100 | | BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 109 | 438 | 0 | clkdv/clk12 | +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ 9. Net wise resources used in clock region X1Y2 ----------------------------------------------- +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ | Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name | +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ | BUFG | --- | no | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clkdv/clkfbin | | BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 0 | 0 | clkdv/clk12 | +-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y17 [get_cells clkdv/buf100] set_property LOC BUFGCTRL_X0Y16 [get_cells clkdv/buf12] set_property LOC BUFGCTRL_X0Y18 [get_cells clkdv/bufclkfb] # Location of IO Clock Primitives # Location of MMCM Clock Primitives set_property LOC MMCME2_ADV_X1Y2 [get_cells clkdv/mmcm] # Location of BUFH Clock Primitives # Location of BUFR Clock Primitives # Location of BUFMR Clock Primitives # Location of PLL Clock Primitives # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X1Y126 [get_ports clk] # Clock net "clkdv/clk100" driven by instance "clkdv/buf100" located at site "BUFGCTRL_X0Y17" #startgroup create_pblock CLKAG_clkdv/clk100 add_cells_to_pblock [get_pblocks CLKAG_clkdv/clk100] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clk100"}]]] resize_pblock [get_pblocks CLKAG_clkdv/clk100] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} #endgroup # Clock net "clkdv/clk12" driven by instance "clkdv/buf12" located at site "BUFGCTRL_X0Y16" #startgroup create_pblock CLKAG_clkdv/clk12 add_cells_to_pblock [get_pblocks CLKAG_clkdv/clk12] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clk12"}]]] resize_pblock [get_pblocks CLKAG_clkdv/clk12] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} #endgroup # Clock net "clkdv/clkout0" driven by instance "clkdv/mmcm" located at site "MMCME2_ADV_X1Y2" #startgroup create_pblock CLKAG_clkdv/clkout0 add_cells_to_pblock [get_pblocks CLKAG_clkdv/clkout0] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=clkdv/buf100} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clkout0"}]]] resize_pblock [get_pblocks CLKAG_clkdv/clkout0] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2} #endgroup