51 lines
2.3 KiB
Plaintext
51 lines
2.3 KiB
Plaintext
Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
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| Date : Wed Apr 22 08:03:16 2015
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| Host : jrpotter running 64-bit major release (build 9200)
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| Command : report_drc
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------------------------------------------------------------------------------------
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max violations: <unlimited>
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Violations found: 3
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2. REPORT DETAILS
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-----------------
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CFGBVS-1#1 Warning
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Missing CFGBVS and CONFIG_VOLTAGE Design Properties
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Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
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set_property CFGBVS value1 [current_design]
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#where value1 is either VCCO or GND
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set_property CONFIG_VOLTAGE value2 [current_design]
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#where value2 is the voltage provided to configuration bank 0
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Refer to the device configuration user guide for more information.
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Related violations: <none>
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REQP-1577#1 Warning
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Clock output buffering
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MMCME2_ADV connectivity violation. The signal clkdv/clkfbout on the clkdv/mmcm/CLKFBOUT pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned and therefore zero hold time at the IO flip-flop(s) may not be met.
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Related violations: <none>
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REQP-1577#2 Warning
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Clock output buffering
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MMCME2_ADV connectivity violation. The signal clkdv/clkout3 on the clkdv/mmcm/CLKOUT3 pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
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Related violations: <none>
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