64 lines
7.0 KiB
Plaintext
64 lines
7.0 KiB
Plaintext
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Determining compilation order of HDL files.
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module fulladder
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module adder
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module comparator
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module addsub
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module logical
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module shifter
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module ALU
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module signExtension
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module xycounter
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module register_file
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module vgatimer
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module smem
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module controller
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module bitmapmem
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module dmem
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module datapath
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module clockdivider_Nexys4
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module debouncer
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module vgadisplaydriver
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module imem
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module memIO
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module mips
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module top
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/imports/src/Lab10_test_sqr.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module mips_test_sqr
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INFO: [VRFC 10-311] analyzing module selfcheck
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INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module project_screentest
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WARNING: [VRFC 10-756] identifier ERROR_pc is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:167]
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WARNING: [VRFC 10-756] identifier ERROR_mem_writedata is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:168]
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WARNING: [VRFC 10-756] identifier ERROR_ReadData1 is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:169]
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WARNING: [VRFC 10-756] identifier ERROR_reg_writedata is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:170]
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WARNING: [VRFC 10-756] identifier ERROR_pcsel is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:171]
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WARNING: [VRFC 10-756] identifier ERROR_smem_addr is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:172]
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WARNING: [VRFC 10-756] identifier ERROR_red is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:173]
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INFO: [VRFC 10-311] analyzing module selfcheck
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WARNING: [VRFC 10-1195] overwriting previous definition of module selfcheck [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:226]
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INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav/glbl.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module glbl
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