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pong/Project.runs/synth_1/top_utilization_synth.rpt

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2015-10-01 13:54:04 +00:00
Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
| Date : Wed Apr 22 08:01:16 2015
| Host : jrpotter running 64-bit major release (build 9200)
| Command : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb
| Design : top
| Device : xc7a100t
| Design State : Synthesized
-------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs* | 1468 | 0 | 63400 | 2.31 |
| LUT as Logic | 1068 | 0 | 63400 | 1.68 |
| LUT as Memory | 400 | 0 | 19000 | 2.10 |
| LUT as Distributed RAM | 400 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 161 | 0 | 126800 | 0.12 |
| Register as Flip Flop | 161 | 0 | 126800 | 0.12 |
| Register as Latch | 0 | 0 | 126800 | 0.00 |
| F7 Muxes | 171 | 0 | 31700 | 0.53 |
| F8 Muxes | 0 | 0 | 15850 | 0.00 |
+----------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 161 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 135 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 135 | 0.00 |
| RAMB18 | 0 | 0 | 270 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 240 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 34 | 0 | 210 | 16.19 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| PHY_CONTROL | 0 | 0 | 6 | 0.00 |
| PHASER_REF | 0 | 0 | 6 | 0.00 |
| OUT_FIFO | 0 | 0 | 24 | 0.00 |
| IN_FIFO | 0 | 0 | 24 | 0.00 |
| IDELAYCTRL | 0 | 0 | 6 | 0.00 |
| IBUFGDS | 0 | 0 | 202 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 |
| ILOGIC | 0 | 0 | 210 | 0.00 |
| OLOGIC | 0 | 0 | 210 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 5 | 0 | 32 | 15.62 |
| BUFIO | 0 | 0 | 24 | 0.00 |
| MMCME2_ADV | 1 | 0 | 6 | 16.66 |
| PLLE2_ADV | 0 | 0 | 6 | 0.00 |
| BUFMRCE | 0 | 0 | 12 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 0 | 0 | 24 | 0.00 |
+------------+------+-------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
7. Primitives
-------------
+------------+------+---------------------+
| Ref Name | Used | Functional Category |
+------------+------+---------------------+
| LUT6 | 560 | LUT |
| RAMD64E | 288 | Distributed Memory |
| LUT5 | 199 | LUT |
| MUXF7 | 171 | MuxFx |
| LUT4 | 167 | LUT |
| FDRE | 161 | Flop & Latch |
| LUT3 | 124 | LUT |
| RAMD32 | 104 | Distributed Memory |
| LUT1 | 104 | LUT |
| LUT2 | 65 | LUT |
| RAMS32 | 56 | Distributed Memory |
| CARRY4 | 36 | CarryLogic |
| OBUF | 30 | IO |
| IBUF | 4 | IO |
| BUFGCTRL | 4 | Clock |
| MMCME2_ADV | 1 | Clock |
| BUFG | 1 | Clock |
+------------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+