58 lines
3.8 KiB
Tcl
58 lines
3.8 KiB
Tcl
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#
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# Synthesis run script generated by Vivado
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#
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set_param gui.test TreeTableDev
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set_param xicom.use_bs_reader 1
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debug::add_scope template.lib 1
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set_msg_config -id {HDL 9-1061} -limit 100000
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set_msg_config -id {HDL 9-1654} -limit 100000
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create_project -in_memory -part xc7a100tcsg324-1
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_property webtalk.parent_dir C:/Users/jrpotter/Documents/Vivado/Project/Project.cache/wt [current_project]
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set_property parent.project_path C:/Users/jrpotter/Documents/Vivado/Project/Project.xpr [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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read_verilog -library xil_defaultlib -sv {
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/initfile.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display640x480.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memory.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv
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}
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read_verilog -library xil_defaultlib {
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v
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C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v
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}
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read_xdc C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc
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set_property used_in_implementation false [get_files C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc]
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catch { write_hwdef -file top.hwdef }
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synth_design -top top -part xc7a100tcsg324-1
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write_checkpoint -noxdef top.dcp
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catch { report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb }
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