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Init
2015-10-01 13:54:04 +00:00
*** Running vivado
with args -log top.vdi -applog -m64 -messageDb vivado.pb -mode batch -source top.tcl -notrace
****** Vivado v2014.4 (64-bit)
**** SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014
**** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
source top.tcl -notrace
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.0/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.1/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/0.9/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.0/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.1/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 173 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.4
Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml
Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml
Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc]
Finished Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 132 instances were transformed.
RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 72 instances
RAM16X1D => RAM32X1D (RAMD32, RAMD32): 8 instances
RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances
RAM32X1D => RAM32X1D (RAMD32, RAMD32): 8 instances
RAM32X1S => RAM32X1S (RAMS32): 32 instances
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 454.113 ; gain = 268.148
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.302 . Memory (MB): peak = 456.133 ; gain = 2.020
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 134e8c1bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.421 . Memory (MB): peak = 943.402 ; gain = 0.000
Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 95 cells.
Phase 2 Constant Propagation | Checksum: 12b01bc4a
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.828 . Memory (MB): peak = 943.402 ; gain = 0.000
Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 251 unconnected nets.
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-11] Eliminated 2 unconnected cells.
Phase 3 Sweep | Checksum: 1e060758c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 943.402 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 1e060758c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 943.402 ; gain = 0.000
Implement Debug Cores | Checksum: 134e8c1bd
Logic Optimization | Checksum: 134e8c1bd
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns.
Ending Power Optimization Task | Checksum: 1e060758c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 943.402 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
24 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 943.402 ; gain = 489.289
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.297 . Memory (MB): peak = 943.402 ; gain = 0.000
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top_drc_opted.rpt.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
Phase 1 Placer Runtime Estimator
Phase 1 Placer Runtime Estimator | Checksum: 129b93edc
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.202 . Memory (MB): peak = 943.402 ; gain = 0.000
Phase 2 Placer Initialization
Phase 2.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 943.402 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 943.402 ; gain = 0.000
Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device
Phase 2.1.1.1 Pre-Place Cells
Phase 2.1.1.1 Pre-Place Cells | Checksum: 85fbccfe
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 943.402 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 2.1.1.2 IO & Clk Clean Up
Phase 2.1.1.2 IO & Clk Clean Up | Checksum: 85fbccfe
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.1.3 Implementation Feasibility check On IDelay
Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: 85fbccfe
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.1.4 Commit IO Placement
Phase 2.1.1.4 Commit IO Placement | Checksum: b418e213
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17336627d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.2 Build Placer Netlist Model
Phase 2.1.2.1 Place Init Design
Phase 2.1.2.1.1 Init Lut Pin Assignment
Phase 2.1.2.1.1 Init Lut Pin Assignment | Checksum: 1b3beedb0
Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.2.1 Place Init Design | Checksum: 1af60e9a5
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.2 Build Placer Netlist Model | Checksum: 1af60e9a5
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.3 Constrain Clocks/Macros
Phase 2.1.3.1 Constrain Global/Regional Clocks
Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 22c265110
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1.3 Constrain Clocks/Macros | Checksum: 22c265110
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2.1 Placer Initialization Core | Checksum: 22c265110
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 2 Placer Initialization | Checksum: 22c265110
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 3 Global Placement
Phase 3 Global Placement | Checksum: 2d993f19b
Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4 Detail Placement
Phase 4.1 Commit Multi Column Macros
Phase 4.1 Commit Multi Column Macros | Checksum: 2d993f19b
Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.2 Commit Most Macros & LUTRAMs
Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 22e4875c4
Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.3 Area Swap Optimization
Phase 4.3 Area Swap Optimization | Checksum: 28b091292
Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.4 updateClock Trees: DP
Phase 4.4 updateClock Trees: DP | Checksum: 28b091292
Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.5 Timing Path Optimizer
Phase 4.5 Timing Path Optimizer | Checksum: 26957948e
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.6 Small Shape Detail Placement
Phase 4.6.1 Commit Small Macros & Core Logic
Phase 4.6.1.1 setBudgets
Phase 4.6.1.1 setBudgets | Checksum: 29621e6b5
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.6.1.2 Commit Slice Clusters
Phase 4.6.1.2 Commit Slice Clusters | Checksum: 30a28b970
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.6.1 Commit Small Macros & Core Logic | Checksum: 30a28b970
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.6.2 Clock Restriction Legalization for Leaf Columns
Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | Checksum: 30a28b970
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins
Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 30a28b970
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.6 Small Shape Detail Placement | Checksum: 30a28b970
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4.7 Re-assign LUT pins
Phase 4.7 Re-assign LUT pins | Checksum: 30a28b970
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 4 Detail Placement | Checksum: 30a28b970
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5 Post Placement Optimization and Clean-Up
Phase 5.1 PCOPT Shape updates
Phase 5.1 PCOPT Shape updates | Checksum: 246db08b2
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.2 Post Commit Optimization
Phase 5.2.1 updateClock Trees: PCOPT
Phase 5.2.1 updateClock Trees: PCOPT | Checksum: 246db08b2
Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.2.2 Post Placement Optimization
Phase 5.2.2.1 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=6.059. For the most accurate timing information please run report_timing.
Phase 5.2.2.1 Post Placement Timing Optimization | Checksum: 286e6ad91
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.2.2 Post Placement Optimization | Checksum: 286e6ad91
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.2 Post Commit Optimization | Checksum: 286e6ad91
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.3 Sweep Clock Roots: Post-Placement
Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 286e6ad91
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.4 Post Placement Cleanup
Phase 5.4 Post Placement Cleanup | Checksum: 286e6ad91
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.5 Placer Reporting
Phase 5.5.1 Restore STA
Phase 5.5.1 Restore STA | Checksum: 286e6ad91
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.5 Placer Reporting | Checksum: 286e6ad91
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5.6 Final Placement Cleanup
Phase 5.6 Final Placement Cleanup | Checksum: 2ed776727
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Phase 5 Post Placement Optimization and Clean-Up | Checksum: 2ed776727
Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
Ending Placer Task | Checksum: 20b640fd1
Time (s): cpu = 00:00:00 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188
INFO: [Common 17-83] Releasing license: Implementation
37 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 965.590 ; gain = 22.188
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.363 . Memory (MB): peak = 965.590 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.172 . Memory (MB): peak = 965.590 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 965.590 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 965.590 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 11f9e7afd
Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1082.340 ; gain = 116.750
Phase 2 Router Initialization
Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 11f9e7afd
Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1084.004 ; gain = 118.414
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 11f9e7afd
Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 1091.496 ; gain = 125.906
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 1b5a28d98
Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 1105.984 ; gain = 140.395
INFO: [Route 35-57] Estimated Timing Summary | WNS=6.09 | TNS=0 | WHS=-0.096 | THS=-2.13 |
Phase 2 Router Initialization | Checksum: 258be7f7a
Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 130551fde
Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 191
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: 138a095ed
Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395
INFO: [Route 35-57] Estimated Timing Summary | WNS=5.74 | TNS=0 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 1ac41c99c
Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 4 Rip-up And Reroute | Checksum: 1ac41c99c
Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 5 Delay CleanUp
Phase 5.1 Update Timing
Phase 5.1 Update Timing | Checksum: 1348a7083
Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395
INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=N/A | THS=N/A |
Phase 5 Delay CleanUp | Checksum: 1348a7083
Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 6 Clock Skew Optimization
Phase 6 Clock Skew Optimization | Checksum: 1348a7083
Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 7 Post Hold Fix
Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: 1699103a9
Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=0.092 | THS=0 |
Phase 7 Post Hold Fix | Checksum: 1699103a9
Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 8 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.316534 %
Global Horizontal Routing Utilization = 0.39649 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 8 Route finalize | Checksum: 17fac11cd
Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 9 Verifying routed nets
Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 17fac11cd
Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: 18e96ff60
Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
Phase 11 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=0.092 | THS=0 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 11 Post Router Timing | Checksum: 18e96ff60
Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
INFO: [Route 35-16] Router Completed Successfully
Routing Is Done.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395
INFO: [Common 17-83] Releasing license: Implementation
50 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 1105.984 ; gain = 140.395
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1105.984 ; gain = 0.000
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top_drc_routed.rpt.
report_drc: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1109.430 ; gain = 3.445
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [Drc 23-20] Rule violation (REQP-1577) Clock output buffering - MMCME2_ADV connectivity violation. The signal clkdv/clkfbout on the clkdv/mmcm/CLKFBOUT pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned and therefore zero hold time at the IO flip-flop(s) may not be met.
WARNING: [Drc 23-20] Rule violation (REQP-1577) Clock output buffering - MMCME2_ADV connectivity violation. The signal clkdv/clkout3 on the clkdv/mmcm/CLKOUT3 pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:33 ; elapsed = 00:01:11 . Memory (MB): peak = 1432.953 ; gain = 322.824
INFO: [Common 17-206] Exiting Vivado at Wed Apr 22 08:04:34 2015...