commit 5daea28de05b199d89f4c574a14d997312f5fbaf Author: Joshua Potter Date: Thu Oct 1 09:54:04 2015 -0400 Init diff --git a/Project.cache/wt/java_command_handlers.wdf b/Project.cache/wt/java_command_handlers.wdf new file mode 100644 index 0000000..354360e --- /dev/null +++ b/Project.cache/wt/java_command_handlers.wdf @@ -0,0 +1,3 @@ +version:1 +70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:30:00:00 +eof:2944385137 diff --git a/Project.cache/wt/synthesis.wdf b/Project.cache/wt/synthesis.wdf new file mode 100644 index 0000000..d690322 --- /dev/null +++ b/Project.cache/wt/synthesis.wdf @@ -0,0 +1,25 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761313030746373673332342d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:746f70:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7365755f70726f74656374:64656661756c743a3a6e6f6e65:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d666c617474656e5f686965726172636879:64656661756c743a3a72656275696c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67617465645f636c6f636b5f636f6e76657273696f6e:64656661756c743a3a6f6666:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646972656374697665:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d72746c:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d62756667:64656661756c743a3a3132:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66616e6f75745f6c696d6974:64656661756c743a3a3130303030:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73687265675f6d696e5f73697a65:64656661756c743a3a33:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6d6f6465:64656661756c743a3a64656661756c74:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d66736d5f65787472616374696f6e:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6b6565705f6571756976616c656e745f726567697374657273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7265736f757263655f73686172696e67:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a303573:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:3638302e3334384d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3530332e3035314d42:00:00 +eof:2776114396 diff --git a/Project.cache/wt/synthesis_details.wdf b/Project.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000..78f8d66 --- /dev/null +++ b/Project.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/Project.cache/wt/webtalk_pa.xml b/Project.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..82554e6 --- /dev/null +++ b/Project.cache/wt/webtalk_pa.xml @@ -0,0 +1,29 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + +
+ + diff --git a/Project.cache/wt/xsim.wdf b/Project.cache/wt/xsim.wdf new file mode 100644 index 0000000..50afb2c --- /dev/null +++ b/Project.cache/wt/xsim.wdf @@ -0,0 +1,4 @@ +version:1 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 +7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 +eof:241934075 diff --git a/Project.hw/hw_1/hw.xml b/Project.hw/hw_1/hw.xml new file mode 100644 index 0000000..daade45 --- /dev/null +++ b/Project.hw/hw_1/hw.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_1.xml b/Project.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_10.xml b/Project.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_100.xml b/Project.runs/.jobs/vrs_config_100.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_100.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_101.xml b/Project.runs/.jobs/vrs_config_101.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_101.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_102.xml b/Project.runs/.jobs/vrs_config_102.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_102.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_103.xml b/Project.runs/.jobs/vrs_config_103.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_103.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_104.xml b/Project.runs/.jobs/vrs_config_104.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_104.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_105.xml b/Project.runs/.jobs/vrs_config_105.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_105.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_106.xml b/Project.runs/.jobs/vrs_config_106.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_106.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_107.xml b/Project.runs/.jobs/vrs_config_107.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_107.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_108.xml b/Project.runs/.jobs/vrs_config_108.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_108.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_109.xml b/Project.runs/.jobs/vrs_config_109.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_109.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_11.xml b/Project.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_110.xml b/Project.runs/.jobs/vrs_config_110.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_110.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_111.xml b/Project.runs/.jobs/vrs_config_111.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_111.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_112.xml b/Project.runs/.jobs/vrs_config_112.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_112.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_113.xml b/Project.runs/.jobs/vrs_config_113.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_113.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_114.xml b/Project.runs/.jobs/vrs_config_114.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_114.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_115.xml b/Project.runs/.jobs/vrs_config_115.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_115.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_116.xml b/Project.runs/.jobs/vrs_config_116.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_116.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_117.xml b/Project.runs/.jobs/vrs_config_117.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_117.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_118.xml b/Project.runs/.jobs/vrs_config_118.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_118.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_12.xml b/Project.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_13.xml b/Project.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_14.xml b/Project.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_15.xml b/Project.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_16.xml b/Project.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_17.xml b/Project.runs/.jobs/vrs_config_17.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_18.xml b/Project.runs/.jobs/vrs_config_18.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_19.xml b/Project.runs/.jobs/vrs_config_19.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_2.xml b/Project.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_20.xml b/Project.runs/.jobs/vrs_config_20.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_21.xml b/Project.runs/.jobs/vrs_config_21.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_22.xml b/Project.runs/.jobs/vrs_config_22.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_22.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_23.xml b/Project.runs/.jobs/vrs_config_23.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_23.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_24.xml b/Project.runs/.jobs/vrs_config_24.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_24.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_25.xml b/Project.runs/.jobs/vrs_config_25.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_25.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_26.xml b/Project.runs/.jobs/vrs_config_26.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_26.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_27.xml b/Project.runs/.jobs/vrs_config_27.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_27.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_28.xml b/Project.runs/.jobs/vrs_config_28.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_28.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_29.xml b/Project.runs/.jobs/vrs_config_29.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_29.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_3.xml b/Project.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_30.xml b/Project.runs/.jobs/vrs_config_30.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_30.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_31.xml b/Project.runs/.jobs/vrs_config_31.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_31.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_32.xml b/Project.runs/.jobs/vrs_config_32.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_32.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_33.xml b/Project.runs/.jobs/vrs_config_33.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_33.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_34.xml b/Project.runs/.jobs/vrs_config_34.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_34.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_35.xml b/Project.runs/.jobs/vrs_config_35.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_35.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_36.xml b/Project.runs/.jobs/vrs_config_36.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_36.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_37.xml b/Project.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_38.xml b/Project.runs/.jobs/vrs_config_38.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_38.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_39.xml b/Project.runs/.jobs/vrs_config_39.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_39.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_4.xml b/Project.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_40.xml b/Project.runs/.jobs/vrs_config_40.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_40.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_41.xml b/Project.runs/.jobs/vrs_config_41.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_41.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_42.xml b/Project.runs/.jobs/vrs_config_42.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_42.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_43.xml b/Project.runs/.jobs/vrs_config_43.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_43.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_44.xml b/Project.runs/.jobs/vrs_config_44.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_44.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_45.xml b/Project.runs/.jobs/vrs_config_45.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_45.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_46.xml b/Project.runs/.jobs/vrs_config_46.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_46.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_47.xml b/Project.runs/.jobs/vrs_config_47.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_47.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_48.xml b/Project.runs/.jobs/vrs_config_48.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_48.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_49.xml b/Project.runs/.jobs/vrs_config_49.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_49.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_5.xml b/Project.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_50.xml b/Project.runs/.jobs/vrs_config_50.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_50.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_51.xml b/Project.runs/.jobs/vrs_config_51.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_51.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_52.xml b/Project.runs/.jobs/vrs_config_52.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_52.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_53.xml b/Project.runs/.jobs/vrs_config_53.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_53.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_54.xml b/Project.runs/.jobs/vrs_config_54.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_54.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_55.xml b/Project.runs/.jobs/vrs_config_55.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_55.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_56.xml b/Project.runs/.jobs/vrs_config_56.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_56.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_57.xml b/Project.runs/.jobs/vrs_config_57.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_57.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_58.xml b/Project.runs/.jobs/vrs_config_58.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_58.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_59.xml b/Project.runs/.jobs/vrs_config_59.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_6.xml b/Project.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_60.xml b/Project.runs/.jobs/vrs_config_60.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_60.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_61.xml b/Project.runs/.jobs/vrs_config_61.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_61.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_62.xml b/Project.runs/.jobs/vrs_config_62.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_62.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_63.xml b/Project.runs/.jobs/vrs_config_63.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_63.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_64.xml b/Project.runs/.jobs/vrs_config_64.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_64.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_65.xml b/Project.runs/.jobs/vrs_config_65.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_65.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_66.xml b/Project.runs/.jobs/vrs_config_66.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_66.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_67.xml b/Project.runs/.jobs/vrs_config_67.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_67.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_68.xml b/Project.runs/.jobs/vrs_config_68.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_68.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_69.xml b/Project.runs/.jobs/vrs_config_69.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_69.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_7.xml b/Project.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_70.xml b/Project.runs/.jobs/vrs_config_70.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_70.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_71.xml b/Project.runs/.jobs/vrs_config_71.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_71.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_72.xml b/Project.runs/.jobs/vrs_config_72.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_72.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_73.xml b/Project.runs/.jobs/vrs_config_73.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_73.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_74.xml b/Project.runs/.jobs/vrs_config_74.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_74.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_75.xml b/Project.runs/.jobs/vrs_config_75.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_75.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_76.xml b/Project.runs/.jobs/vrs_config_76.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_76.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_77.xml b/Project.runs/.jobs/vrs_config_77.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_77.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_78.xml b/Project.runs/.jobs/vrs_config_78.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_78.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_79.xml b/Project.runs/.jobs/vrs_config_79.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_79.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_8.xml b/Project.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..1297fc0 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_80.xml b/Project.runs/.jobs/vrs_config_80.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_80.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_81.xml b/Project.runs/.jobs/vrs_config_81.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_81.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_82.xml b/Project.runs/.jobs/vrs_config_82.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_82.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_83.xml b/Project.runs/.jobs/vrs_config_83.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_83.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_84.xml b/Project.runs/.jobs/vrs_config_84.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_84.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_85.xml b/Project.runs/.jobs/vrs_config_85.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_85.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_86.xml b/Project.runs/.jobs/vrs_config_86.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_86.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_87.xml b/Project.runs/.jobs/vrs_config_87.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_87.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_88.xml b/Project.runs/.jobs/vrs_config_88.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_88.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_89.xml b/Project.runs/.jobs/vrs_config_89.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_89.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_9.xml b/Project.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_90.xml b/Project.runs/.jobs/vrs_config_90.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_90.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_91.xml b/Project.runs/.jobs/vrs_config_91.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_91.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_92.xml b/Project.runs/.jobs/vrs_config_92.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_92.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_93.xml b/Project.runs/.jobs/vrs_config_93.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_93.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_94.xml b/Project.runs/.jobs/vrs_config_94.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_94.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_95.xml b/Project.runs/.jobs/vrs_config_95.xml new file mode 100644 index 0000000..c0e2283 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_95.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/.jobs/vrs_config_96.xml b/Project.runs/.jobs/vrs_config_96.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_96.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_97.xml b/Project.runs/.jobs/vrs_config_97.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_97.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_98.xml b/Project.runs/.jobs/vrs_config_98.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_98.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/.jobs/vrs_config_99.xml b/Project.runs/.jobs/vrs_config_99.xml new file mode 100644 index 0000000..c878bb2 --- /dev/null +++ b/Project.runs/.jobs/vrs_config_99.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/Project.runs/impl_1/.Vivado_Implementation.queue.rst b/Project.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/impl_1/.init_design.begin.rst b/Project.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..d1f9375 --- /dev/null +++ b/Project.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/impl_1/.init_design.end.rst b/Project.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/impl_1/.opt_design.begin.rst b/Project.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..d1f9375 --- /dev/null +++ b/Project.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/impl_1/.opt_design.end.rst b/Project.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/impl_1/.place_design.begin.rst b/Project.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..d1f9375 --- /dev/null +++ b/Project.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/impl_1/.place_design.end.rst b/Project.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/impl_1/.route_design.begin.rst b/Project.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..d1f9375 --- /dev/null +++ b/Project.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/impl_1/.route_design.end.rst b/Project.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/impl_1/.vivado.begin.rst b/Project.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..18f9210 --- /dev/null +++ b/Project.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/impl_1/.vivado.end.rst b/Project.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/impl_1/.write_bitstream.begin.rst b/Project.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..d1f9375 --- /dev/null +++ b/Project.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/impl_1/.write_bitstream.end.rst b/Project.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/impl_1/ISEWrap.js b/Project.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..8a98177 --- /dev/null +++ b/Project.runs/impl_1/ISEWrap.js @@ -0,0 +1,196 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.close(); +} + +function ISEOpenFile( ISEFilename ) { + + var ISEFullPath = ISERunDir + "/" + ISEFilename; + return ISEFileSys.OpenTextFile( ISEFullPath, 8, true ); +} diff --git a/Project.runs/impl_1/ISEWrap.sh b/Project.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..2b3ebe0 --- /dev/null +++ b/Project.runs/impl_1/ISEWrap.sh @@ -0,0 +1,62 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL diff --git a/Project.runs/impl_1/gen_run.xml b/Project.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..1167a20 --- /dev/null +++ b/Project.runs/impl_1/gen_run.xml @@ -0,0 +1,384 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Project.runs/impl_1/htr.txt b/Project.runs/impl_1/htr.txt new file mode 100644 index 0000000..1b2370a --- /dev/null +++ b/Project.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log top.vdi -applog -m64 -messageDb vivado.pb -mode batch -source top.tcl -notrace diff --git a/Project.runs/impl_1/init_design.pb b/Project.runs/impl_1/init_design.pb new file mode 100644 index 0000000..0ffea60 Binary files /dev/null and b/Project.runs/impl_1/init_design.pb differ diff --git a/Project.runs/impl_1/opt_design.pb b/Project.runs/impl_1/opt_design.pb new file mode 100644 index 0000000..e80d7dd Binary files /dev/null and b/Project.runs/impl_1/opt_design.pb differ diff --git a/Project.runs/impl_1/place_design.pb b/Project.runs/impl_1/place_design.pb new file mode 100644 index 0000000..9d6e9af Binary files /dev/null and b/Project.runs/impl_1/place_design.pb differ diff --git a/Project.runs/impl_1/project.wdf b/Project.runs/impl_1/project.wdf new file mode 100644 index 0000000..48059e9 --- /dev/null +++ b/Project.runs/impl_1/project.wdf @@ -0,0 +1,17 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3334:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:707270726f6a656374:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e666967706172746974696f6e636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7265636f6e6669676d6f64756c65636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:686470726f6a656374:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:706172746974696f6e636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3566356437646464333263623463306362323839363033653432366339666564:506172656e742050412070726f6a656374204944:00 +eof:603943905 diff --git a/Project.runs/impl_1/route_design.pb b/Project.runs/impl_1/route_design.pb new file mode 100644 index 0000000..a18a0db Binary files /dev/null and b/Project.runs/impl_1/route_design.pb differ diff --git a/Project.runs/impl_1/rundef.js b/Project.runs/impl_1/rundef.js new file mode 100644 index 0000000..9c6a682 --- /dev/null +++ b/Project.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2014.4/bin;"; +} else { + PathVal = "C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2014.4/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log top.vdi -applog -m64 -messageDb vivado.pb -mode batch -source top.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Project.runs/impl_1/runme.bat b/Project.runs/impl_1/runme.bat new file mode 100644 index 0000000..b93f7db --- /dev/null +++ b/Project.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Project.runs/impl_1/runme.log b/Project.runs/impl_1/runme.log new file mode 100644 index 0000000..e76741f --- /dev/null +++ b/Project.runs/impl_1/runme.log @@ -0,0 +1,508 @@ + +*** Running vivado + with args -log top.vdi -applog -m64 -messageDb vivado.pb -mode batch -source top.tcl -notrace + + +****** Vivado v2014.4 (64-bit) + **** SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 + **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 + ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. + +source top.tcl -notrace +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.0/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.1/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/0.9/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.0/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.1/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 173 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2014.4 +Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml +Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml +Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml +Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml... +Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml +Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml +Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +Finished Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 132 instances were transformed. + RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 72 instances + RAM16X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances + RAM32X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32X1S => RAM32X1S (RAMS32): 32 instances + +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 454.113 ; gain = 268.148 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.302 . Memory (MB): peak = 456.133 ; gain = 2.020 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks + +Starting Logic Optimization Task + +Phase 1 Retarget + +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 134e8c1bd + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.421 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 2 Constant Propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-10] Eliminated 95 cells. +Phase 2 Constant Propagation | Checksum: 12b01bc4a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.828 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 3 Sweep +INFO: [Opt 31-12] Eliminated 251 unconnected nets. +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +INFO: [Opt 31-11] Eliminated 2 unconnected cells. +Phase 3 Sweep | Checksum: 1e060758c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 943.402 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e060758c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 943.402 ; gain = 0.000 +Implement Debug Cores | Checksum: 134e8c1bd +Logic Optimization | Checksum: 134e8c1bd + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns. +Ending Power Optimization Task | Checksum: 1e060758c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 943.402 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 943.402 ; gain = 489.289 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.297 . Memory (MB): peak = 943.402 ; gain = 0.000 +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top_drc_opted.rpt. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Runtime Estimator +Phase 1 Placer Runtime Estimator | Checksum: 129b93edc + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.202 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 2 Placer Initialization + +Phase 2.1 Placer Initialization Core +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 943.402 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device + +Phase 2.1.1.1 Pre-Place Cells +Phase 2.1.1.1 Pre-Place Cells | Checksum: 85fbccfe + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 943.402 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 2.1.1.2 IO & Clk Clean Up +Phase 2.1.1.2 IO & Clk Clean Up | Checksum: 85fbccfe + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.1.3 Implementation Feasibility check On IDelay +Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: 85fbccfe + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.1.4 Commit IO Placement +Phase 2.1.1.4 Commit IO Placement | Checksum: b418e213 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17336627d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.2 Build Placer Netlist Model + +Phase 2.1.2.1 Place Init Design + +Phase 2.1.2.1.1 Init Lut Pin Assignment +Phase 2.1.2.1.1 Init Lut Pin Assignment | Checksum: 1b3beedb0 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.2.1 Place Init Design | Checksum: 1af60e9a5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.2 Build Placer Netlist Model | Checksum: 1af60e9a5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.3 Constrain Clocks/Macros + +Phase 2.1.3.1 Constrain Global/Regional Clocks +Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.3 Constrain Clocks/Macros | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1 Placer Initialization Core | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2 Placer Initialization | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 3 Global Placement +Phase 3 Global Placement | Checksum: 2d993f19b + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4 Detail Placement + +Phase 4.1 Commit Multi Column Macros +Phase 4.1 Commit Multi Column Macros | Checksum: 2d993f19b + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.2 Commit Most Macros & LUTRAMs +Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 22e4875c4 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.3 Area Swap Optimization +Phase 4.3 Area Swap Optimization | Checksum: 28b091292 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.4 updateClock Trees: DP +Phase 4.4 updateClock Trees: DP | Checksum: 28b091292 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.5 Timing Path Optimizer +Phase 4.5 Timing Path Optimizer | Checksum: 26957948e + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6 Small Shape Detail Placement + +Phase 4.6.1 Commit Small Macros & Core Logic + +Phase 4.6.1.1 setBudgets +Phase 4.6.1.1 setBudgets | Checksum: 29621e6b5 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6.1.2 Commit Slice Clusters +Phase 4.6.1.2 Commit Slice Clusters | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 4.6.1 Commit Small Macros & Core Logic | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6.2 Clock Restriction Legalization for Leaf Columns +Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins +Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 4.6 Small Shape Detail Placement | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.7 Re-assign LUT pins +Phase 4.7 Re-assign LUT pins | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 4 Detail Placement | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5 Post Placement Optimization and Clean-Up + +Phase 5.1 PCOPT Shape updates +Phase 5.1 PCOPT Shape updates | Checksum: 246db08b2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.2 Post Commit Optimization + +Phase 5.2.1 updateClock Trees: PCOPT +Phase 5.2.1 updateClock Trees: PCOPT | Checksum: 246db08b2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.2.2 Post Placement Optimization + +Phase 5.2.2.1 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=6.059. For the most accurate timing information please run report_timing. +Phase 5.2.2.1 Post Placement Timing Optimization | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5.2.2 Post Placement Optimization | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5.2 Post Commit Optimization | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.3 Sweep Clock Roots: Post-Placement +Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.4 Post Placement Cleanup +Phase 5.4 Post Placement Cleanup | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.5 Placer Reporting + +Phase 5.5.1 Restore STA +Phase 5.5.1 Restore STA | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5.5 Placer Reporting | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.6 Final Placement Cleanup +Phase 5.6 Final Placement Cleanup | Checksum: 2ed776727 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5 Post Placement Optimization and Clean-Up | Checksum: 2ed776727 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Ending Placer Task | Checksum: 20b640fd1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +INFO: [Common 17-83] Releasing license: Implementation +37 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 965.590 ; gain = 22.188 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.363 . Memory (MB): peak = 965.590 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.172 . Memory (MB): peak = 965.590 ; gain = 0.000 +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 965.590 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 965.590 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 11f9e7afd + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1082.340 ; gain = 116.750 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 11f9e7afd + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1084.004 ; gain = 118.414 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 11f9e7afd + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 1091.496 ; gain = 125.906 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 1b5a28d98 + +Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=6.09 | TNS=0 | WHS=-0.096 | THS=-2.13 | + +Phase 2 Router Initialization | Checksum: 258be7f7a + +Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 130551fde + +Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 191 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 + +Phase 4.1.1 Update Timing +Phase 4.1.1 Update Timing | Checksum: 138a095ed + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.74 | TNS=0 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 1ac41c99c + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 +Phase 4 Rip-up And Reroute | Checksum: 1ac41c99c + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 5 Delay CleanUp + +Phase 5.1 Update Timing +Phase 5.1 Update Timing | Checksum: 1348a7083 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=N/A | THS=N/A | + +Phase 5 Delay CleanUp | Checksum: 1348a7083 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 6 Clock Skew Optimization +Phase 6 Clock Skew Optimization | Checksum: 1348a7083 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 7 Post Hold Fix + +Phase 7.1 Update Timing +Phase 7.1 Update Timing | Checksum: 1699103a9 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=0.092 | THS=0 | + +Phase 7 Post Hold Fix | Checksum: 1699103a9 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.316534 % + Global Horizontal Routing Utilization = 0.39649 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 17fac11cd + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 17fac11cd + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 18e96ff60 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 11 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=0.092 | THS=0 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 11 Post Router Timing | Checksum: 18e96ff60 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-16] Router Completed Successfully + +Routing Is Done. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Common 17-83] Releasing license: Implementation +50 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 1105.984 ; gain = 140.395 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1105.984 ; gain = 0.000 +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top_drc_routed.rpt. +report_drc: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1109.430 ; gain = 3.445 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [Drc 23-27] Running DRC with 2 threads +WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [Drc 23-20] Rule violation (REQP-1577) Clock output buffering - MMCME2_ADV connectivity violation. The signal clkdv/clkfbout on the clkdv/mmcm/CLKFBOUT pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned and therefore zero hold time at the IO flip-flop(s) may not be met. +WARNING: [Drc 23-20] Rule violation (REQP-1577) Clock output buffering - MMCME2_ADV connectivity violation. The signal clkdv/clkout3 on the clkdv/mmcm/CLKOUT3 pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +write_bitstream: Time (s): cpu = 00:00:33 ; elapsed = 00:01:11 . Memory (MB): peak = 1432.953 ; gain = 322.824 +INFO: [Common 17-206] Exiting Vivado at Wed Apr 22 08:04:34 2015... diff --git a/Project.runs/impl_1/runme.sh b/Project.runs/impl_1/runme.sh new file mode 100644 index 0000000..f96672e --- /dev/null +++ b/Project.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2014.4/bin +else + PATH=C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2014.4/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD=`dirname "$0"` +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log top.vdi -applog -m64 -messageDb vivado.pb -mode batch -source top.tcl -notrace + + diff --git a/Project.runs/impl_1/top.bit b/Project.runs/impl_1/top.bit new file mode 100644 index 0000000..71cfa83 Binary files /dev/null and b/Project.runs/impl_1/top.bit differ diff --git a/Project.runs/impl_1/top.tcl b/Project.runs/impl_1/top.tcl new file mode 100644 index 0000000..36ca9e0 --- /dev/null +++ b/Project.runs/impl_1/top.tcl @@ -0,0 +1,138 @@ +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {HDL 9-1061} -limit 100000 +set_msg_config -id {HDL 9-1654} -limit 100000 + +start_step init_design +set rc [catch { + create_msg_db init_design.pb + set_param gui.test TreeTableDev + set_param xicom.use_bs_reader 1 + debug::add_scope template.lib 1 + set_property design_mode GateLvl [current_fileset] + set_property webtalk.parent_dir C:/Users/jrpotter/Documents/Vivado/Project/Project.cache/wt [current_project] + set_property parent.project_path C:/Users/jrpotter/Documents/Vivado/Project/Project.xpr [current_project] + set_property ip_repo_paths c:/Users/jrpotter/Documents/Vivado/Project/Project.cache/ip [current_project] + set_property ip_output_repo c:/Users/jrpotter/Documents/Vivado/Project/Project.cache/ip [current_project] + add_files -quiet C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/synth_1/top.dcp + read_xdc C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc + link_design -top top -part xc7a100tcsg324-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design +} + +start_step opt_design +set rc [catch { + create_msg_db opt_design.pb + catch {write_debug_probes -quiet -force debug_nets} + opt_design + write_checkpoint -force top_opt.dcp + catch {report_drc -file top_drc_opted.rpt} + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design +} + +start_step place_design +set rc [catch { + create_msg_db place_design.pb + place_design + write_checkpoint -force top_placed.dcp + catch { report_io -file top_io_placed.rpt } + catch { report_clock_utilization -file top_clock_utilization_placed.rpt } + catch { report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb } + catch { report_control_sets -verbose -file top_control_sets_placed.rpt } + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design +} + +start_step route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force top_routed.dcp + catch { report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb } + catch { report_timing_summary -warn_on_violation -max_paths 10 -file top_timing_summary_routed.rpt -rpx top_timing_summary_routed.rpx } + catch { report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb } + catch { report_route_status -file top_route_status.rpt -pb top_route_status.pb } + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + step_failed route_design + return -code error $RESULT +} else { + end_step route_design +} + +start_step write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + write_bitstream -force top.bit + if { [file exists C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/synth_1/top.hwdef] } { + catch { write_sysdef -hwdef C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/synth_1/top.hwdef -bitfile top.bit -meminfo top.mmi -file top.sysdef } + } + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream +} + diff --git a/Project.runs/impl_1/top.vdi b/Project.runs/impl_1/top.vdi new file mode 100644 index 0000000..93a7129 --- /dev/null +++ b/Project.runs/impl_1/top.vdi @@ -0,0 +1,506 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 08:01:21 2015 +# Process ID: 212 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.0/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.1/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/0.9/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.0/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.1/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 173 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2014.4 +Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml +Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml +Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml +Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml... +Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml +Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml +Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +Finished Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 132 instances were transformed. + RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 72 instances + RAM16X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances + RAM32X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32X1S => RAM32X1S (RAMS32): 32 instances + +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 454.113 ; gain = 268.148 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.302 . Memory (MB): peak = 456.133 ; gain = 2.020 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 134e8c1bd + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.421 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 2 Constant Propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-10] Eliminated 95 cells. +Phase 2 Constant Propagation | Checksum: 12b01bc4a + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.828 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 3 Sweep +INFO: [Opt 31-12] Eliminated 251 unconnected nets. +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +INFO: [Opt 31-11] Eliminated 2 unconnected cells. +Phase 3 Sweep | Checksum: 1e060758c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 943.402 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1e060758c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 943.402 ; gain = 0.000 +Implement Debug Cores | Checksum: 134e8c1bd +Logic Optimization | Checksum: 134e8c1bd + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns. +Ending Power Optimization Task | Checksum: 1e060758c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 943.402 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:28 . Memory (MB): peak = 943.402 ; gain = 489.289 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.297 . Memory (MB): peak = 943.402 ; gain = 0.000 +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top_drc_opted.rpt. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Runtime Estimator +Phase 1 Placer Runtime Estimator | Checksum: 129b93edc + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.202 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 2 Placer Initialization + +Phase 2.1 Placer Initialization Core +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 943.402 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 943.402 ; gain = 0.000 + +Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device + +Phase 2.1.1.1 Pre-Place Cells +Phase 2.1.1.1 Pre-Place Cells | Checksum: 85fbccfe + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.499 . Memory (MB): peak = 943.402 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 2.1.1.2 IO & Clk Clean Up +Phase 2.1.1.2 IO & Clk Clean Up | Checksum: 85fbccfe + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.1.3 Implementation Feasibility check On IDelay +Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: 85fbccfe + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.1.4 Commit IO Placement +Phase 2.1.1.4 Commit IO Placement | Checksum: b418e213 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17336627d + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.2 Build Placer Netlist Model + +Phase 2.1.2.1 Place Init Design + +Phase 2.1.2.1.1 Init Lut Pin Assignment +Phase 2.1.2.1.1 Init Lut Pin Assignment | Checksum: 1b3beedb0 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.2.1 Place Init Design | Checksum: 1af60e9a5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.2 Build Placer Netlist Model | Checksum: 1af60e9a5 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 2.1.3 Constrain Clocks/Macros + +Phase 2.1.3.1 Constrain Global/Regional Clocks +Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1.3 Constrain Clocks/Macros | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2.1 Placer Initialization Core | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 2 Placer Initialization | Checksum: 22c265110 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 3 Global Placement +Phase 3 Global Placement | Checksum: 2d993f19b + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4 Detail Placement + +Phase 4.1 Commit Multi Column Macros +Phase 4.1 Commit Multi Column Macros | Checksum: 2d993f19b + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.2 Commit Most Macros & LUTRAMs +Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 22e4875c4 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.3 Area Swap Optimization +Phase 4.3 Area Swap Optimization | Checksum: 28b091292 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.4 updateClock Trees: DP +Phase 4.4 updateClock Trees: DP | Checksum: 28b091292 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.5 Timing Path Optimizer +Phase 4.5 Timing Path Optimizer | Checksum: 26957948e + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6 Small Shape Detail Placement + +Phase 4.6.1 Commit Small Macros & Core Logic + +Phase 4.6.1.1 setBudgets +Phase 4.6.1.1 setBudgets | Checksum: 29621e6b5 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6.1.2 Commit Slice Clusters +Phase 4.6.1.2 Commit Slice Clusters | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 4.6.1 Commit Small Macros & Core Logic | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6.2 Clock Restriction Legalization for Leaf Columns +Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins +Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 4.6 Small Shape Detail Placement | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 4.7 Re-assign LUT pins +Phase 4.7 Re-assign LUT pins | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 4 Detail Placement | Checksum: 30a28b970 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5 Post Placement Optimization and Clean-Up + +Phase 5.1 PCOPT Shape updates +Phase 5.1 PCOPT Shape updates | Checksum: 246db08b2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.2 Post Commit Optimization + +Phase 5.2.1 updateClock Trees: PCOPT +Phase 5.2.1 updateClock Trees: PCOPT | Checksum: 246db08b2 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.2.2 Post Placement Optimization + +Phase 5.2.2.1 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=6.059. For the most accurate timing information please run report_timing. +Phase 5.2.2.1 Post Placement Timing Optimization | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5.2.2 Post Placement Optimization | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5.2 Post Commit Optimization | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.3 Sweep Clock Roots: Post-Placement +Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.4 Post Placement Cleanup +Phase 5.4 Post Placement Cleanup | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.5 Placer Reporting + +Phase 5.5.1 Restore STA +Phase 5.5.1 Restore STA | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5.5 Placer Reporting | Checksum: 286e6ad91 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 + +Phase 5.6 Final Placement Cleanup +Phase 5.6 Final Placement Cleanup | Checksum: 2ed776727 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Phase 5 Post Placement Optimization and Clean-Up | Checksum: 2ed776727 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +Ending Placer Task | Checksum: 20b640fd1 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:10 . Memory (MB): peak = 965.590 ; gain = 22.188 +INFO: [Common 17-83] Releasing license: Implementation +37 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 965.590 ; gain = 22.188 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.363 . Memory (MB): peak = 965.590 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.172 . Memory (MB): peak = 965.590 ; gain = 0.000 +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 965.590 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 965.590 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 11f9e7afd + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1082.340 ; gain = 116.750 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 11f9e7afd + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 1084.004 ; gain = 118.414 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 11f9e7afd + +Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 1091.496 ; gain = 125.906 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 1b5a28d98 + +Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=6.09 | TNS=0 | WHS=-0.096 | THS=-2.13 | + +Phase 2 Router Initialization | Checksum: 258be7f7a + +Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 130551fde + +Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 191 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 + +Phase 4.1.1 Update Timing +Phase 4.1.1 Update Timing | Checksum: 138a095ed + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.74 | TNS=0 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 1ac41c99c + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 +Phase 4 Rip-up And Reroute | Checksum: 1ac41c99c + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 5 Delay CleanUp + +Phase 5.1 Update Timing +Phase 5.1 Update Timing | Checksum: 1348a7083 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=N/A | THS=N/A | + +Phase 5 Delay CleanUp | Checksum: 1348a7083 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 6 Clock Skew Optimization +Phase 6 Clock Skew Optimization | Checksum: 1348a7083 + +Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 7 Post Hold Fix + +Phase 7.1 Update Timing +Phase 7.1 Update Timing | Checksum: 1699103a9 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=0.092 | THS=0 | + +Phase 7 Post Hold Fix | Checksum: 1699103a9 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.316534 % + Global Horizontal Routing Utilization = 0.39649 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 17fac11cd + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 17fac11cd + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 18e96ff60 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 + +Phase 11 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.84 | TNS=0 | WHS=0.092 | THS=0 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 11 Post Router Timing | Checksum: 18e96ff60 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Route 35-16] Router Completed Successfully + +Routing Is Done. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:50 . Memory (MB): peak = 1105.984 ; gain = 140.395 +INFO: [Common 17-83] Releasing license: Implementation +50 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 1105.984 ; gain = 140.395 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.812 . Memory (MB): peak = 1105.984 ; gain = 0.000 +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top_drc_routed.rpt. +report_drc: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1109.430 ; gain = 3.445 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [Drc 23-27] Running DRC with 2 threads +WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +WARNING: [Drc 23-20] Rule violation (REQP-1577) Clock output buffering - MMCME2_ADV connectivity violation. The signal clkdv/clkfbout on the clkdv/mmcm/CLKFBOUT pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned and therefore zero hold time at the IO flip-flop(s) may not be met. +WARNING: [Drc 23-20] Rule violation (REQP-1577) Clock output buffering - MMCME2_ADV connectivity violation. The signal clkdv/clkout3 on the clkdv/mmcm/CLKOUT3 pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 3 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +write_bitstream: Time (s): cpu = 00:00:33 ; elapsed = 00:01:11 . Memory (MB): peak = 1432.953 ; gain = 322.824 +INFO: [Common 17-206] Exiting Vivado at Wed Apr 22 08:04:34 2015... diff --git a/Project.runs/impl_1/top_4464.backup.vdi b/Project.runs/impl_1/top_4464.backup.vdi new file mode 100644 index 0000000..a2de3ab --- /dev/null +++ b/Project.runs/impl_1/top_4464.backup.vdi @@ -0,0 +1,469 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Tue Apr 21 21:01:57 2015 +# Process ID: 5944 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.0/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.1/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/0.9/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.0/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.1/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Netlist 29-17] Analyzing 173 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2014.4 +Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml +Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml +Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml +Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml... +Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml +Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml +Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +Finished Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 132 instances were transformed. + RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 72 instances + RAM16X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances + RAM32X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32X1S => RAM32X1S (RAMS32): 32 instances + +link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 454.090 ; gain = 268.148 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 456.383 ; gain = 2.293 +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: ebc4a2f8 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 944.027 ; gain = 0.000 + +Phase 2 Constant Propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-10] Eliminated 95 cells. +Phase 2 Constant Propagation | Checksum: 1419ce2f5 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.178 . Memory (MB): peak = 944.027 ; gain = 0.000 + +Phase 3 Sweep +INFO: [Opt 31-12] Eliminated 251 unconnected nets. +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +INFO: [Opt 31-11] Eliminated 2 unconnected cells. +Phase 3 Sweep | Checksum: 1fb38e3e2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.323 . Memory (MB): peak = 944.027 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1fb38e3e2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.331 . Memory (MB): peak = 944.027 ; gain = 0.000 +Implement Debug Cores | Checksum: ebc4a2f8 +Logic Optimization | Checksum: ebc4a2f8 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns. +Ending Power Optimization Task | Checksum: 1fb38e3e2 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 944.027 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +24 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 944.027 ; gain = 489.938 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.064 . Memory (MB): peak = 944.027 ; gain = 0.000 +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top_drc_opted.rpt. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Runtime Estimator +Phase 1 Placer Runtime Estimator | Checksum: 1207a0250 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 944.027 ; gain = 0.000 + +Phase 2 Placer Initialization + +Phase 2.1 Placer Initialization Core +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 944.027 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 944.027 ; gain = 0.000 + +Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device + +Phase 2.1.1.1 Pre-Place Cells +Phase 2.1.1.1 Pre-Place Cells | Checksum: 85fbccfe + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.084 . Memory (MB): peak = 944.027 ; gain = 0.000 +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 2.1.1.2 IO & Clk Clean Up +Phase 2.1.1.2 IO & Clk Clean Up | Checksum: 85fbccfe + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 2.1.1.3 Implementation Feasibility check On IDelay +Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: 85fbccfe + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 2.1.1.4 Commit IO Placement +Phase 2.1.1.4 Commit IO Placement | Checksum: b418e213 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17541c2ed + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 2.1.2 Build Placer Netlist Model + +Phase 2.1.2.1 Place Init Design + +Phase 2.1.2.1.1 Init Lut Pin Assignment +Phase 2.1.2.1.1 Init Lut Pin Assignment | Checksum: 1a8afd7f9 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 2.1.2.1 Place Init Design | Checksum: 1b9bffa85 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 2.1.2 Build Placer Netlist Model | Checksum: 1b9bffa85 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 2.1.3 Constrain Clocks/Macros + +Phase 2.1.3.1 Constrain Global/Regional Clocks +Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 2368561f0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 2.1.3 Constrain Clocks/Macros | Checksum: 2368561f0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 2.1 Placer Initialization Core | Checksum: 2368561f0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 2 Placer Initialization | Checksum: 2368561f0 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 3 Global Placement +Phase 3 Global Placement | Checksum: 2a66362b6 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4 Detail Placement + +Phase 4.1 Commit Multi Column Macros +Phase 4.1 Commit Multi Column Macros | Checksum: 2a66362b6 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.2 Commit Most Macros & LUTRAMs +Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 1a54c9b52 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.3 Area Swap Optimization +Phase 4.3 Area Swap Optimization | Checksum: 17b0626ed + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.4 updateClock Trees: DP +Phase 4.4 updateClock Trees: DP | Checksum: 17b0626ed + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.5 Timing Path Optimizer +Phase 4.5 Timing Path Optimizer | Checksum: 1c041dc5b + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.6 Small Shape Detail Placement + +Phase 4.6.1 Commit Small Macros & Core Logic + +Phase 4.6.1.1 setBudgets +Phase 4.6.1.1 setBudgets | Checksum: 140eeea36 + +Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.6.1.2 Commit Slice Clusters +Phase 4.6.1.2 Commit Slice Clusters | Checksum: 17411c840 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 4.6.1 Commit Small Macros & Core Logic | Checksum: 17411c840 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.6.2 Clock Restriction Legalization for Leaf Columns +Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | Checksum: 17411c840 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins +Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 17411c840 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 4.6 Small Shape Detail Placement | Checksum: 17411c840 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 4.7 Re-assign LUT pins +Phase 4.7 Re-assign LUT pins | Checksum: 17411c840 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 4 Detail Placement | Checksum: 17411c840 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 5 Post Placement Optimization and Clean-Up + +Phase 5.1 PCOPT Shape updates +Phase 5.1 PCOPT Shape updates | Checksum: 1d2f5ca24 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 5.2 Post Commit Optimization + +Phase 5.2.1 updateClock Trees: PCOPT +Phase 5.2.1 updateClock Trees: PCOPT | Checksum: 1d2f5ca24 + +Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 5.2.2 Post Placement Optimization + +Phase 5.2.2.1 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=5.825. For the most accurate timing information please run report_timing. +Phase 5.2.2.1 Post Placement Timing Optimization | Checksum: 1d10c8aec + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 5.2.2 Post Placement Optimization | Checksum: 1d10c8aec + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 5.2 Post Commit Optimization | Checksum: 1d10c8aec + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 5.3 Sweep Clock Roots: Post-Placement +Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 1d10c8aec + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 5.4 Post Placement Cleanup +Phase 5.4 Post Placement Cleanup | Checksum: 1d10c8aec + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 5.5 Placer Reporting + +Phase 5.5.1 Restore STA +Phase 5.5.1 Restore STA | Checksum: 1d10c8aec + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 5.5 Placer Reporting | Checksum: 1d10c8aec + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 + +Phase 5.6 Final Placement Cleanup +Phase 5.6 Final Placement Cleanup | Checksum: 1d5365216 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 +Phase 5 Post Placement Optimization and Clean-Up | Checksum: 1d5365216 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 +Ending Placer Task | Checksum: 12ad93528 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:08 . Memory (MB): peak = 966.293 ; gain = 22.266 +INFO: [Common 17-83] Releasing license: Implementation +37 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 966.293 ; gain = 22.266 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.403 . Memory (MB): peak = 966.293 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.068 . Memory (MB): peak = 966.293 ; gain = 0.000 +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.089 . Memory (MB): peak = 966.293 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 966.293 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [Drc 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: 12fe929b9 + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:41 . Memory (MB): peak = 1075.691 ; gain = 109.398 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: 12fe929b9 + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:41 . Memory (MB): peak = 1076.195 ; gain = 109.902 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 12fe929b9 + +Time (s): cpu = 00:00:47 ; elapsed = 00:00:41 . Memory (MB): peak = 1084.918 ; gain = 118.625 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 2953af8e6 + +Time (s): cpu = 00:00:49 ; elapsed = 00:00:43 . Memory (MB): peak = 1098.434 ; gain = 132.141 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.85 | TNS=0 | WHS=-0.096 | THS=-1.81 | + +Phase 2 Router Initialization | Checksum: 274689372 + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:43 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 2588f987e + +Time (s): cpu = 00:00:50 ; elapsed = 00:00:43 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 219 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 + +Phase 4.1.1 Update Timing +Phase 4.1.1 Update Timing | Checksum: d503c172 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:44 . Memory (MB): peak = 1098.434 ; gain = 132.141 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.4 | TNS=0 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 13cb2fd75 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:44 . Memory (MB): peak = 1098.434 ; gain = 132.141 +Phase 4 Rip-up And Reroute | Checksum: 13cb2fd75 + +Time (s): cpu = 00:00:52 ; elapsed = 00:00:44 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 5 Delay CleanUp + +Phase 5.1 Update Timing +Phase 5.1 Update Timing | Checksum: 16ba8eafe + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.5 | TNS=0 | WHS=N/A | THS=N/A | + +Phase 5 Delay CleanUp | Checksum: 16ba8eafe + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 6 Clock Skew Optimization +Phase 6 Clock Skew Optimization | Checksum: 16ba8eafe + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 7 Post Hold Fix + +Phase 7.1 Update Timing +Phase 7.1 Update Timing | Checksum: 12dd0bfa6 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.5 | TNS=0 | WHS=0.168 | THS=0 | + +Phase 7 Post Hold Fix | Checksum: ccfa1943 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.3171 % + Global Horizontal Routing Utilization = 0.411978 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 165409364 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 165409364 + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: f3e7028d + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 + +Phase 11 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=5.5 | TNS=0 | WHS=0.168 | THS=0 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 11 Post Router Timing | Checksum: f3e7028d + +Time (s): cpu = 00:00:53 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 +INFO: [Route 35-16] Router Completed Successfully + +Routing Is Done. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:45 . Memory (MB): peak = 1098.434 ; gain = 132.141 +INFO: [Common 17-83] Releasing license: Implementation +50 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:54 ; elapsed = 00:00:46 . Memory (MB): peak = 1098.434 ; gain = 132.141 +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.471 . Memory (MB): peak = 1098.434 ; gain = 0.000 diff --git a/Project.runs/impl_1/top_4828.backup.vdi b/Project.runs/impl_1/top_4828.backup.vdi new file mode 100644 index 0000000..ff79c5d --- /dev/null +++ b/Project.runs/impl_1/top_4828.backup.vdi @@ -0,0 +1,19 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Tue Apr 21 15:52:26 2015 +# Process ID: 6092 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace + +*** Halting run - EA reset detected *** + + + + while executing +"start_step write_bitstream" + (file "top.tcl" line 48) +INFO: [Common 17-206] Exiting Vivado at Tue Apr 21 15:52:28 2015... diff --git a/Project.runs/impl_1/top_clock_utilization_placed.rpt b/Project.runs/impl_1/top_clock_utilization_placed.rpt new file mode 100644 index 0000000..bdf4e4e --- /dev/null +++ b/Project.runs/impl_1/top_clock_utilization_placed.rpt @@ -0,0 +1,163 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:02:12 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_clock_utilization -file top_clock_utilization_placed.rpt +| Design : top +| Device : xc7a100t +------------------------------------------------------------------------------------ + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Details of Global Clocks +3. Details of Regional Clocks +4. Details of Multi-Regional Clocks +5. Details of I/O Clocks +6. Details of Local Clocks +7. Clock Regions : Key Resource Utilization +8. Net wise resources used in clock region X1Y1 +9. Net wise resources used in clock region X1Y2 + +1. Clock Primitive Utilization +------------------------------ + ++-------+------+-----------+-----------+ +| Type | Used | Available | Num Fixed | ++-------+------+-----------+-----------+ +| BUFG | 3 | 32 | 0 | +| BUFH | 0 | 96 | 0 | +| BUFIO | 0 | 24 | 0 | +| MMCM | 1 | 6 | 0 | +| PLL | 0 | 6 | 0 | +| BUFR | 0 | 24 | 0 | +| BUFMR | 0 | 12 | 0 | ++-------+------+-----------+-----------+ + + +2. Details of Global Clocks +--------------------------- + ++-------+----------------+---------------+--------------+-------+---------------+-----------+ +| | | | Num Loads | | | | ++-------+----------------+---------------+------+-------+-------+---------------+-----------+ +| Index | BUFG Cell | Net Name | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) | ++-------+----------------+---------------+------+-------+-------+---------------+-----------+ +| 1 | clkdv/bufclkfb | clkdv/clkfbin | 1 | 1 | no | 1.711 | 0.086 | +| 2 | clkdv/buf100 | clkdv/clk100 | 26 | 8 | no | 1.881 | 0.153 | +| 3 | clkdv/buf12 | clkdv/clk12 | 570 | 144 | no | 1.887 | 0.257 | ++-------+----------------+---------------+------+-------+-------+---------------+-----------+ + + ++-------+------------+----------------+--------------+-------+---------------+-----------+ +| | | | Num Loads | | | | ++-------+------------+----------------+------+-------+-------+---------------+-----------+ +| Index | MMCM Cell | Net Name | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) | ++-------+------------+----------------+------+-------+-------+---------------+-----------+ +| 1 | clkdv/mmcm | clkdv/clkfbout | 1 | 1 | no | 1.719 | 0.086 | +| 2 | clkdv/mmcm | clkdv/clkout3 | 1 | 1 | no | 1.719 | 0.086 | +| 3 | clkdv/mmcm | clkdv/clkout0 | 4 | 2 | no | 1.719 | 1.593 | ++-------+------------+----------------+------+-------+-------+---------------+-----------+ + + +3. Details of Regional Clocks +----------------------------- + +4. Details of Multi-Regional Clocks +----------------------------------- + +5. Details of I/O Clocks +------------------------ + +6. Details of Local Clocks +-------------------------- + +7. Clock Regions : Key Resource Utilization +------------------------------------------- + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E1 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 20800 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12000 | 0 | 2200 | 0 | 40 | 0 | 20 | 0 | 40 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 16000 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 135 | 15200 | 438 | 2600 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 16000 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 26 | 15200 | 0 | 2600 | 0 | 60 | 0 | 30 | 0 | 40 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 20800 | 0 | 2400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 10800 | 0 | 2000 | 0 | 30 | 0 | 15 | 0 | 40 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* RAMB36 site can be used as two RAMB18/FIFO18 sites + + +8. Net wise resources used in clock region X1Y1 +----------------------------------------------- + ++-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ +| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name | ++-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ +| BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | clkdv/clk100 | +| BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 109 | 438 | 0 | clkdv/clk12 | ++-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ + + +9. Net wise resources used in clock region X1Y2 +----------------------------------------------- + ++-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ +| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s | Clock Net Name | ++-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ +| BUFG | --- | no | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clkdv/clkfbin | +| BUFGCTRL | --- | no | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 0 | 0 | clkdv/clk12 | ++-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+----------------+ + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y17 [get_cells clkdv/buf100] +set_property LOC BUFGCTRL_X0Y16 [get_cells clkdv/buf12] +set_property LOC BUFGCTRL_X0Y18 [get_cells clkdv/bufclkfb] + +# Location of IO Clock Primitives + +# Location of MMCM Clock Primitives +set_property LOC MMCME2_ADV_X1Y2 [get_cells clkdv/mmcm] + +# Location of BUFH Clock Primitives + +# Location of BUFR Clock Primitives + +# Location of BUFMR Clock Primitives + +# Location of PLL Clock Primitives + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X1Y126 [get_ports clk] + +# Clock net "clkdv/clk100" driven by instance "clkdv/buf100" located at site "BUFGCTRL_X0Y17" +#startgroup +create_pblock CLKAG_clkdv/clk100 +add_cells_to_pblock [get_pblocks CLKAG_clkdv/clk100] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clk100"}]]] +resize_pblock [get_pblocks CLKAG_clkdv/clk100] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} +#endgroup + +# Clock net "clkdv/clk12" driven by instance "clkdv/buf12" located at site "BUFGCTRL_X0Y16" +#startgroup +create_pblock CLKAG_clkdv/clk12 +add_cells_to_pblock [get_pblocks CLKAG_clkdv/clk12] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clk12"}]]] +resize_pblock [get_pblocks CLKAG_clkdv/clk12] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3} +#endgroup + +# Clock net "clkdv/clkout0" driven by instance "clkdv/mmcm" located at site "MMCME2_ADV_X1Y2" +#startgroup +create_pblock CLKAG_clkdv/clkout0 +add_cells_to_pblock [get_pblocks CLKAG_clkdv/clkout0] [get_cells -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=clkdv/buf100} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clkdv/clkout0"}]]] +resize_pblock [get_pblocks CLKAG_clkdv/clkout0] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2} +#endgroup diff --git a/Project.runs/impl_1/top_control_sets_placed.rpt b/Project.runs/impl_1/top_control_sets_placed.rpt new file mode 100644 index 0000000..ce13d2b --- /dev/null +++ b/Project.runs/impl_1/top_control_sets_placed.rpt @@ -0,0 +1,78 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:02:13 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file top_control_sets_placed.rpt +| Design : top +| Device : xc7a100t +------------------------------------------------------------------------------------ + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Flip-Flop Distribution +3. Detailed Control Set Information + +1. Summary +---------- + ++-------------------------------------------------------------------+-------+ +| Status | Count | ++-------------------------------------------------------------------+-------+ +| Number of unique control sets | 25 | +| Minimum Number of register sites lost to control set restrictions | 39 | ++-------------------------------------------------------------------+-------+ + + +2. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 26 | 10 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 73 | 28 | +| Yes | No | No | 18 | 4 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 44 | 12 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +3. Detailed Control Set Information +----------------------------------- + ++----------------+-------------------------------------+-------------------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+-------------------------------------+-------------------------------------+------------------+----------------+ +| clkdv/clk100 | | | 1 | 2 | +| clkdv/clkout0 | | | 1 | 3 | +| clkdv/clk12 | io/kmem/n_0_count[3]_i_1 | io/kmem/count0 | 1 | 4 | +| clkdv/clk12 | io/kmem/count0 | | 1 | 8 | +| clkdv/clk100 | displaydriver/timer/xy/n_0_x[9]_i_1 | displaydriver/timer/xy/n_0_y[9]_i_1 | 3 | 10 | +| clkdv/clk12 | io/kmem/n_0_bits[9]_i_1 | | 3 | 10 | +| clkdv/clk12 | mips/dp/rf/O11 | | 3 | 11 | +| clkdv/clk12 | mips/dp/rf/O13 | | 3 | 11 | +| clkdv/clk100 | displaydriver/timer/xy/Every4thTick | displaydriver/timer/xy/n_0_x[9]_i_1 | 4 | 14 | +| clkdv/clk12 | io/kmem/count0 | io/kmem/n_0_keyb_char[23]_i_1 | 4 | 16 | +| clkdv/clk12 | | io/kmem/clear | 5 | 20 | +| clkdv/clk12 | | | 8 | 21 | +| clkdv/clk12 | | rbouncer/n_0_count[0]_i_1__0 | 6 | 21 | +| clkdv/clk12 | | rbouncer/SR[0] | 17 | 32 | +| clkdv/clk12 | mips/dp/rf/O27 | | 9 | 32 | +| clkdv/clk12 | mips/dp/rf/O28 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O29 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O32 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O33 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O34 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O35 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O37 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O38 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/O41 | | 8 | 32 | +| clkdv/clk12 | mips/dp/rf/wr | | 12 | 96 | ++----------------+-------------------------------------+-------------------------------------+------------------+----------------+ + + diff --git a/Project.runs/impl_1/top_drc_opted.rpt b/Project.runs/impl_1/top_drc_opted.rpt new file mode 100644 index 0000000..4caa054 --- /dev/null +++ b/Project.runs/impl_1/top_drc_opted.rpt @@ -0,0 +1,50 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:02:00 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_drc +------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +REQP-1577#1 Warning +Clock output buffering +MMCME2_ADV connectivity violation. The signal clkdv/clkfbout on the clkdv/mmcm/CLKFBOUT pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned and therefore zero hold time at the IO flip-flop(s) may not be met. +Related violations: + +REQP-1577#2 Warning +Clock output buffering +MMCME2_ADV connectivity violation. The signal clkdv/clkout3 on the clkdv/mmcm/CLKOUT3 pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + + diff --git a/Project.runs/impl_1/top_drc_routed.pb b/Project.runs/impl_1/top_drc_routed.pb new file mode 100644 index 0000000..cb5bb32 Binary files /dev/null and b/Project.runs/impl_1/top_drc_routed.pb differ diff --git a/Project.runs/impl_1/top_drc_routed.rpt b/Project.runs/impl_1/top_drc_routed.rpt new file mode 100644 index 0000000..fa3b0f6 --- /dev/null +++ b/Project.runs/impl_1/top_drc_routed.rpt @@ -0,0 +1,50 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:03:16 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_drc +------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 + +2. REPORT DETAILS +----------------- +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + +REQP-1577#1 Warning +Clock output buffering +MMCME2_ADV connectivity violation. The signal clkdv/clkfbout on the clkdv/mmcm/CLKFBOUT pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned and therefore zero hold time at the IO flip-flop(s) may not be met. +Related violations: + +REQP-1577#2 Warning +Clock output buffering +MMCME2_ADV connectivity violation. The signal clkdv/clkout3 on the clkdv/mmcm/CLKOUT3 pin of clkdv/mmcm does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + + diff --git a/Project.runs/impl_1/top_io_placed.rpt b/Project.runs/impl_1/top_io_placed.rpt new file mode 100644 index 0000000..d3ca818 --- /dev/null +++ b/Project.runs/impl_1/top_io_placed.rpt @@ -0,0 +1,364 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:02:12 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_io -file top_io_placed.rpt +| Design : top +| Device : xc7a100t +| Speed File : -1 +| Package : csg324 +------------------------------------------------------------------------------------ + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 34 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+----------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | Vref | Signal Integrity | ++------------+----------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+------+------------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | +| A3 | red[0] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| A4 | red[3] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| A5 | green[1] | High Range | IO_L3N_T0_DQS_AD5N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| A6 | green[3] | High Range | IO_L3P_T0_DQS_AD5P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | +| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | +| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | +| B2 | ps2_data | High Range | IO_L10N_T1_AD15N_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | PULLUP | | NONE | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | +| B4 | red[1] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | +| B6 | green[2] | High Range | IO_L2N_T0_AD12N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| B7 | blue[0] | High Range | IO_L2P_T0_AD12P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | +| B11 | hsync | High Range | IO_L4P_T0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| B12 | vsync | High Range | IO_L3N_T0_DQS_AD1N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | +| C5 | red[2] | High Range | IO_L1N_T0_AD4N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| C6 | green[0] | High Range | IO_L1P_T0_AD4P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| C7 | blue[1] | High Range | IO_L4N_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | +| C12 | reset | High Range | IO_L3P_T0_DQS_AD1P_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | NONE | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | +| D7 | blue[2] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| D8 | blue[3] | High Range | IO_L4P_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | +| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | +| E3 | clk | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | NONE | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | +| F4 | ps2_clk | High Range | IO_L13P_T2_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | PULLUP | | NONE | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | +| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | +| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | +| K3 | segments[3] | High Range | IO_L2P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | +| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | +| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | +| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | +| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | +| L1 | digitselect[6] | High Range | IO_L1P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | +| L3 | segments[7] | High Range | IO_L2N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| L4 | segments[4] | High Range | IO_L5N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| L5 | segments[5] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| L6 | segments[1] | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | +| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | +| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | +| M1 | digitselect[7] | High Range | IO_L1N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| M2 | segments[2] | High Range | IO_L4N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| M3 | digitselect[2] | High Range | IO_L4P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| M4 | segments[0] | High Range | IO_L16P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | +| M6 | digitselect[1] | High Range | IO_L18P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | +| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | +| N1 | segments[6] | High Range | IO_L3N_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| N2 | digitselect[4] | High Range | IO_L3P_T0_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | +| N4 | digitselect[5] | High Range | IO_L16N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| N5 | digitselect[3] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| N6 | digitselect[0] | High Range | IO_L18N_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | NONE | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | +| P2 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | +| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | +| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | +| P5 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | +| R1 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | +| R2 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | +| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | +| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | +| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | +| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | +| R8 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | +| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | +| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | +| T5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | +| T6 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | +| T8 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | +| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | +| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | +| U1 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | +| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | +| U3 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | +| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | +| U6 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | +| U7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | +| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | +| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | +| V1 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | +| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | +| V4 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | +| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | +| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | +| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | +| V9 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | ++------------+----------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/Project.runs/impl_1/top_opt.dcp b/Project.runs/impl_1/top_opt.dcp new file mode 100644 index 0000000..59accd6 Binary files /dev/null and b/Project.runs/impl_1/top_opt.dcp differ diff --git a/Project.runs/impl_1/top_placed.dcp b/Project.runs/impl_1/top_placed.dcp new file mode 100644 index 0000000..95687ff Binary files /dev/null and b/Project.runs/impl_1/top_placed.dcp differ diff --git a/Project.runs/impl_1/top_power_routed.rpt b/Project.runs/impl_1/top_power_routed.rpt new file mode 100644 index 0000000..815964f --- /dev/null +++ b/Project.runs/impl_1/top_power_routed.rpt @@ -0,0 +1,294 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:03:19 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb +| Design : top +| Device : xc7a100tcsg324-1 +| Design State : Routed +| Grade : commercial +| Process : typical +| Characterization : Production +----------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------+ +| Total On-Chip Power (W) | 0.212 | +| Dynamic (W) | 0.115 | +| Device Static (W) | 0.097 | +| Effective TJA (C/W) | 4.6 | +| Max Ambient (C) | 84.0 | +| Junction Temperature (C) | 26.0 | +| Confidence Level | Medium | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------+ + + +1.1 On-Chip Components +---------------------- + ++--------------------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++--------------------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.001 | 8 | --- | --- | +| Slice Logic | 0.002 | 1948 | --- | --- | +| LUT as Logic | 0.001 | 961 | 63400 | 1.51 | +| LUT as Distributed RAM | <0.001 | 386 | 19000 | 2.03 | +| F7/F8 Muxes | <0.001 | 171 | 63400 | 0.26 | +| CARRY4 | <0.001 | 36 | 15850 | 0.22 | +| Register | <0.001 | 161 | 126800 | 0.12 | +| Others | 0.000 | 18 | --- | --- | +| Signals | 0.001 | 1477 | --- | --- | +| MMCM | 0.106 | 1 | 6 | 16.66 | +| I/O | 0.004 | 34 | 210 | 16.19 | +| Static Power | 0.097 | | | | +| Total | 0.212 | | | | ++--------------------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.020 | 0.005 | 0.015 | +| Vccaux | 1.800 | 0.077 | 0.059 | 0.018 | +| Vcco33 | 3.300 | 0.005 | 0.001 | 0.004 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Medium | More than 25% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 4.6 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------------+----------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------------+----------------+-----------------+ +| clkfbout | clkdv/clkfbout | 10.0 | +| clkout0 | clkdv/clkout0 | 10.0 | +| clkout3 | clkdv/clkout3 | 80.0 | +| sys_clk_pin | clk | 10.0 | ++-------------+----------------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------------------------------+-----------+ +| Name | Power (W) | ++------------------------------+-----------+ +| top | 0.115 | +| clkdv | 0.107 | +| displaydriver | <0.001 | +| timer | <0.001 | +| xy | <0.001 | +| io | 0.001 | +| disp | <0.001 | +| dmem | <0.001 | +| mem_reg_0_31_0_0 | <0.001 | +| mem_reg_0_31_10_10 | <0.001 | +| mem_reg_0_31_11_11 | <0.001 | +| mem_reg_0_31_12_12 | <0.001 | +| mem_reg_0_31_13_13 | <0.001 | +| mem_reg_0_31_14_14 | <0.001 | +| mem_reg_0_31_15_15 | <0.001 | +| mem_reg_0_31_16_16 | <0.001 | +| mem_reg_0_31_17_17 | <0.001 | +| mem_reg_0_31_18_18 | <0.001 | +| mem_reg_0_31_19_19 | <0.001 | +| mem_reg_0_31_1_1 | <0.001 | +| mem_reg_0_31_20_20 | <0.001 | +| mem_reg_0_31_21_21 | <0.001 | +| mem_reg_0_31_22_22 | <0.001 | +| mem_reg_0_31_23_23 | <0.001 | +| mem_reg_0_31_24_24 | <0.001 | +| mem_reg_0_31_25_25 | <0.001 | +| mem_reg_0_31_26_26 | <0.001 | +| mem_reg_0_31_27_27 | <0.001 | +| mem_reg_0_31_28_28 | <0.001 | +| mem_reg_0_31_29_29 | <0.001 | +| mem_reg_0_31_2_2 | <0.001 | +| mem_reg_0_31_30_30 | <0.001 | +| mem_reg_0_31_31_31 | <0.001 | +| mem_reg_0_31_3_3 | <0.001 | +| mem_reg_0_31_4_4 | <0.001 | +| mem_reg_0_31_5_5 | <0.001 | +| mem_reg_0_31_6_6 | <0.001 | +| mem_reg_0_31_7_7 | <0.001 | +| mem_reg_0_31_8_8 | <0.001 | +| mem_reg_0_31_9_9 | <0.001 | +| kmem | <0.001 | +| smem | <0.001 | +| mem_reg_0_127_0_0 | <0.001 | +| mem_reg_0_127_1_1 | <0.001 | +| mem_reg_0_127_2_2 | <0.001 | +| mem_reg_0_127_3_3 | <0.001 | +| mem_reg_0_127_4_4 | <0.001 | +| mem_reg_0_127_5_5 | <0.001 | +| mem_reg_0_127_6_6 | <0.001 | +| mem_reg_0_127_7_7 | <0.001 | +| mem_reg_0_15_0_0 | <0.001 | +| mem_reg_0_15_0_0__0 | <0.001 | +| mem_reg_0_15_0_0__1 | <0.001 | +| mem_reg_0_15_0_0__2 | <0.001 | +| mem_reg_0_15_0_0__3 | <0.001 | +| mem_reg_0_15_0_0__4 | <0.001 | +| mem_reg_0_15_0_0__5 | <0.001 | +| mem_reg_0_15_0_0__6 | <0.001 | +| mem_reg_0_31_0_0 | <0.001 | +| mem_reg_0_31_0_0__0 | <0.001 | +| mem_reg_0_31_0_0__1 | <0.001 | +| mem_reg_0_31_0_0__2 | <0.001 | +| mem_reg_0_31_0_0__3 | <0.001 | +| mem_reg_0_31_0_0__4 | <0.001 | +| mem_reg_0_31_0_0__5 | <0.001 | +| mem_reg_0_31_0_0__6 | <0.001 | +| mem_reg_1024_1151_0_0 | <0.001 | +| mem_reg_1024_1151_1_1 | <0.001 | +| mem_reg_1024_1151_2_2 | <0.001 | +| mem_reg_1024_1151_3_3 | <0.001 | +| mem_reg_1024_1151_4_4 | <0.001 | +| mem_reg_1024_1151_5_5 | <0.001 | +| mem_reg_1024_1151_6_6 | <0.001 | +| mem_reg_1024_1151_7_7 | <0.001 | +| mem_reg_128_255_0_0 | <0.001 | +| mem_reg_128_255_1_1 | <0.001 | +| mem_reg_128_255_2_2 | <0.001 | +| mem_reg_128_255_3_3 | <0.001 | +| mem_reg_128_255_4_4 | <0.001 | +| mem_reg_128_255_5_5 | <0.001 | +| mem_reg_128_255_6_6 | <0.001 | +| mem_reg_128_255_7_7 | <0.001 | +| mem_reg_256_383_0_0 | <0.001 | +| mem_reg_256_383_1_1 | <0.001 | +| mem_reg_256_383_2_2 | <0.001 | +| mem_reg_256_383_3_3 | <0.001 | +| mem_reg_256_383_4_4 | <0.001 | +| mem_reg_256_383_5_5 | <0.001 | +| mem_reg_256_383_6_6 | <0.001 | +| mem_reg_256_383_7_7 | <0.001 | +| mem_reg_384_511_0_0 | <0.001 | +| mem_reg_384_511_1_1 | <0.001 | +| mem_reg_384_511_2_2 | <0.001 | +| mem_reg_384_511_3_3 | <0.001 | +| mem_reg_384_511_4_4 | <0.001 | +| mem_reg_384_511_5_5 | <0.001 | +| mem_reg_384_511_6_6 | <0.001 | +| mem_reg_384_511_7_7 | <0.001 | +| mem_reg_512_639_0_0 | <0.001 | +| mem_reg_512_639_1_1 | <0.001 | +| mem_reg_512_639_2_2 | <0.001 | +| mem_reg_512_639_3_3 | <0.001 | +| mem_reg_512_639_4_4 | <0.001 | +| mem_reg_512_639_5_5 | <0.001 | +| mem_reg_512_639_6_6 | <0.001 | +| mem_reg_512_639_7_7 | <0.001 | +| mem_reg_640_767_0_0 | <0.001 | +| mem_reg_640_767_1_1 | <0.001 | +| mem_reg_640_767_2_2 | <0.001 | +| mem_reg_640_767_3_3 | <0.001 | +| mem_reg_640_767_4_4 | <0.001 | +| mem_reg_640_767_5_5 | <0.001 | +| mem_reg_640_767_6_6 | <0.001 | +| mem_reg_640_767_7_7 | <0.001 | +| mem_reg_768_895_0_0 | <0.001 | +| mem_reg_768_895_1_1 | <0.001 | +| mem_reg_768_895_2_2 | <0.001 | +| mem_reg_768_895_3_3 | <0.001 | +| mem_reg_768_895_4_4 | <0.001 | +| mem_reg_768_895_5_5 | <0.001 | +| mem_reg_768_895_6_6 | <0.001 | +| mem_reg_768_895_7_7 | <0.001 | +| mem_reg_896_1023_0_0 | <0.001 | +| mem_reg_896_1023_1_1 | <0.001 | +| mem_reg_896_1023_2_2 | <0.001 | +| mem_reg_896_1023_3_3 | <0.001 | +| mem_reg_896_1023_4_4 | <0.001 | +| mem_reg_896_1023_5_5 | <0.001 | +| mem_reg_896_1023_6_6 | <0.001 | +| mem_reg_896_1023_7_7 | <0.001 | +| mips | 0.002 | +| dp | 0.002 | +| rf | 0.002 | +| rf_reg_r1_0_31_0_5 | <0.001 | +| rf_reg_r1_0_31_12_17 | <0.001 | +| rf_reg_r1_0_31_18_23 | <0.001 | +| rf_reg_r1_0_31_24_29 | <0.001 | +| rf_reg_r1_0_31_30_31 | <0.001 | +| rf_reg_r1_0_31_6_11 | <0.001 | +| rf_reg_r2_0_31_0_5 | <0.001 | +| rf_reg_r2_0_31_12_17 | <0.001 | +| rf_reg_r2_0_31_18_23 | <0.001 | +| rf_reg_r2_0_31_24_29 | <0.001 | +| rf_reg_r2_0_31_30_31 | <0.001 | +| rf_reg_r2_0_31_6_11 | <0.001 | +| rbouncer | <0.001 | ++------------------------------+-----------+ + + diff --git a/Project.runs/impl_1/top_power_summary_routed.pb b/Project.runs/impl_1/top_power_summary_routed.pb new file mode 100644 index 0000000..e712cac Binary files /dev/null and b/Project.runs/impl_1/top_power_summary_routed.pb differ diff --git a/Project.runs/impl_1/top_route_status.pb b/Project.runs/impl_1/top_route_status.pb new file mode 100644 index 0000000..7e42940 Binary files /dev/null and b/Project.runs/impl_1/top_route_status.pb differ diff --git a/Project.runs/impl_1/top_route_status.rpt b/Project.runs/impl_1/top_route_status.rpt new file mode 100644 index 0000000..4977b2a --- /dev/null +++ b/Project.runs/impl_1/top_route_status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 2104 : + # of nets not needing routing.......... : 618 : + # of internally routed nets........ : 541 : + # of nets with no loads............ : 77 : + # of routable nets..................... : 1486 : + # of fully routed nets............. : 1486 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/Project.runs/impl_1/top_routed.dcp b/Project.runs/impl_1/top_routed.dcp new file mode 100644 index 0000000..b86e3b2 Binary files /dev/null and b/Project.runs/impl_1/top_routed.dcp differ diff --git a/Project.runs/impl_1/top_timing_summary_routed.rpt b/Project.runs/impl_1/top_timing_summary_routed.rpt new file mode 100644 index 0000000..29ba2d2 --- /dev/null +++ b/Project.runs/impl_1/top_timing_summary_routed.rpt @@ -0,0 +1,3334 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:03:18 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_timing_summary -warn_on_violation -max_paths 10 -file top_timing_summary_routed.rpt -rpx top_timing_summary_routed.rpx +| Design : top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.14 2014-09-11 +| Temperature Grade : C +---------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking unexpandable_clocks +13. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 2 pins that are not constrained for maximum delay due to constant clock. (MEDIUM) + + +5. checking no_input_delay +-------------------------- + There are 3 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There are 29 ports with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 2 generated clocks that are not connected to a clock source. (HIGH) + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking unexpandable_clocks +-------------------------------- + There are 0 unexpandable clock pairs. + + +13. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 5.865 0.000 0 3939 0.094 0.000 0 3939 3.000 0.000 0 609 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +sys_clk_pin {0.000 5.000} 10.000 100.000 + clkfbout {0.000 5.000} 10.000 100.000 + clkout0 {0.000 5.000} 10.000 100.000 + clkout1 {0.000 10.000} 20.000 50.000 + clkout2 {0.000 20.000} 40.000 25.000 + clkout3 {0.000 40.000} 80.000 12.500 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +sys_clk_pin 3.000 0.000 0 1 + clkfbout 7.845 0.000 0 3 + clkout0 5.865 0.000 0 78 0.192 0.000 0 78 4.500 0.000 0 31 + clkout1 18.751 0.000 0 1 + clkout2 38.751 0.000 0 1 + clkout3 52.402 0.000 0 3860 0.094 0.000 0 3860 38.750 0.000 0 572 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clkout0 clkout3 7.215 0.000 0 1 0.392 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_clk_pin + To Clock: sys_clk_pin + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_clk_pin +Waveform: { 0 5 } +Period: 10.000 +Sources: { clk } + +Check Type Corner Lib Pin Reference Pin Required Actual Slack Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKIN1 +Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKIN1 +High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkfbout + To Clock: clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkfbout +Waveform: { 0 5 } +Period: 10.000 +Sources: { clkdv/mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required Actual Slack Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y18 clkdv/bufclkfb/I +Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKFBIN +Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKFBOUT +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKFBIN +Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKFBOUT + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkout0 + To Clock: clkout0 + +Setup : 0 Failing Endpoints, Worst Slack 5.865ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.192ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 5.865ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[3]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/x_reg[0]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.537ns (logic 0.897ns (25.360%) route 2.640ns (74.640%)) + Logic Levels: 2 (LUT3=1 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.417ns = ( 8.583 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.601ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.478 -0.338 r displaydriver/timer/xy/x_reg[3]/Q + net (fo=7, routed) 1.040 0.702 displaydriver/timer/xy/bmem_addr[3] + SLICE_X80Y96 LUT5 (Prop_lut5_I0_O) 0.295 0.997 f displaydriver/timer/xy/x[9]_i_5/O + net (fo=7, routed) 0.865 1.862 displaydriver/timer/xy/n_0_x[9]_i_5 + SLICE_X79Y97 LUT3 (Prop_lut3_I2_O) 0.124 1.986 r displaydriver/timer/xy/x[9]_i_1/O + net (fo=24, routed) 0.735 2.721 displaydriver/timer/xy/n_0_x[9]_i_1 + SLICE_X80Y96 FDRE r displaydriver/timer/xy/x_reg[0]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.603 8.583 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[0]/C + clock pessimism 0.601 9.184 + clock uncertainty -0.074 9.111 + SLICE_X80Y96 FDRE (Setup_fdre_C_R) -0.524 8.587 displaydriver/timer/xy/x_reg[0] + ------------------------------------------------------------------- + required time 8.587 + arrival time -2.721 + ------------------------------------------------------------------- + slack 5.865 + +Slack (MET) : 5.865ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[3]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/x_reg[3]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.537ns (logic 0.897ns (25.360%) route 2.640ns (74.640%)) + Logic Levels: 2 (LUT3=1 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.417ns = ( 8.583 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.601ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.478 -0.338 r displaydriver/timer/xy/x_reg[3]/Q + net (fo=7, routed) 1.040 0.702 displaydriver/timer/xy/bmem_addr[3] + SLICE_X80Y96 LUT5 (Prop_lut5_I0_O) 0.295 0.997 f displaydriver/timer/xy/x[9]_i_5/O + net (fo=7, routed) 0.865 1.862 displaydriver/timer/xy/n_0_x[9]_i_5 + SLICE_X79Y97 LUT3 (Prop_lut3_I2_O) 0.124 1.986 r displaydriver/timer/xy/x[9]_i_1/O + net (fo=24, routed) 0.735 2.721 displaydriver/timer/xy/n_0_x[9]_i_1 + SLICE_X80Y96 FDRE r displaydriver/timer/xy/x_reg[3]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.603 8.583 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[3]/C + clock pessimism 0.601 9.184 + clock uncertainty -0.074 9.111 + SLICE_X80Y96 FDRE (Setup_fdre_C_R) -0.524 8.587 displaydriver/timer/xy/x_reg[3] + ------------------------------------------------------------------- + required time 8.587 + arrival time -2.721 + ------------------------------------------------------------------- + slack 5.865 + +Slack (MET) : 5.865ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[3]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/x_reg[5]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.537ns (logic 0.897ns (25.360%) route 2.640ns (74.640%)) + Logic Levels: 2 (LUT3=1 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.417ns = ( 8.583 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.601ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.478 -0.338 r displaydriver/timer/xy/x_reg[3]/Q + net (fo=7, routed) 1.040 0.702 displaydriver/timer/xy/bmem_addr[3] + SLICE_X80Y96 LUT5 (Prop_lut5_I0_O) 0.295 0.997 f displaydriver/timer/xy/x[9]_i_5/O + net (fo=7, routed) 0.865 1.862 displaydriver/timer/xy/n_0_x[9]_i_5 + SLICE_X79Y97 LUT3 (Prop_lut3_I2_O) 0.124 1.986 r displaydriver/timer/xy/x[9]_i_1/O + net (fo=24, routed) 0.735 2.721 displaydriver/timer/xy/n_0_x[9]_i_1 + SLICE_X80Y96 FDRE r displaydriver/timer/xy/x_reg[5]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.603 8.583 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + clock pessimism 0.601 9.184 + clock uncertainty -0.074 9.111 + SLICE_X80Y96 FDRE (Setup_fdre_C_R) -0.524 8.587 displaydriver/timer/xy/x_reg[5] + ------------------------------------------------------------------- + required time 8.587 + arrival time -2.721 + ------------------------------------------------------------------- + slack 5.865 + +Slack (MET) : 5.865ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[3]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/x_reg[5]_rep/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.537ns (logic 0.897ns (25.360%) route 2.640ns (74.640%)) + Logic Levels: 2 (LUT3=1 LUT5=1) + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.417ns = ( 8.583 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.601ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.478 -0.338 r displaydriver/timer/xy/x_reg[3]/Q + net (fo=7, routed) 1.040 0.702 displaydriver/timer/xy/bmem_addr[3] + SLICE_X80Y96 LUT5 (Prop_lut5_I0_O) 0.295 0.997 f displaydriver/timer/xy/x[9]_i_5/O + net (fo=7, routed) 0.865 1.862 displaydriver/timer/xy/n_0_x[9]_i_5 + SLICE_X79Y97 LUT3 (Prop_lut3_I2_O) 0.124 1.986 r displaydriver/timer/xy/x[9]_i_1/O + net (fo=24, routed) 0.735 2.721 displaydriver/timer/xy/n_0_x[9]_i_1 + SLICE_X80Y96 FDRE r displaydriver/timer/xy/x_reg[5]_rep/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.603 8.583 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]_rep/C + clock pessimism 0.601 9.184 + clock uncertainty -0.074 9.111 + SLICE_X80Y96 FDRE (Setup_fdre_C_R) -0.524 8.587 displaydriver/timer/xy/x_reg[5]_rep + ------------------------------------------------------------------- + required time 8.587 + arrival time -2.721 + ------------------------------------------------------------------- + slack 5.865 + +Slack (MET) : 5.884ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[2]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.578ns (logic 0.890ns (24.873%) route 2.688ns (75.127%)) + Logic Levels: 3 (LUT6=3) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.410ns = ( 8.590 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.518 -0.298 f displaydriver/timer/xy/x_reg[5]/Q + net (fo=71, routed) 1.267 0.969 displaydriver/timer/xy/Q[1] + SLICE_X83Y93 LUT6 (Prop_lut6_I3_O) 0.124 1.093 r displaydriver/timer/xy/y[9]_i_6/O + net (fo=1, routed) 0.299 1.392 displaydriver/timer/xy/n_0_y[9]_i_6 + SLICE_X82Y94 LUT6 (Prop_lut6_I5_O) 0.124 1.516 r displaydriver/timer/xy/y[9]_i_4/O + net (fo=1, routed) 0.387 1.903 displaydriver/timer/xy/n_0_y[9]_i_4 + SLICE_X81Y94 LUT6 (Prop_lut6_I5_O) 0.124 2.027 r displaydriver/timer/xy/y[9]_i_1/O + net (fo=10, routed) 0.736 2.763 displaydriver/timer/xy/n_0_y[9]_i_1 + SLICE_X82Y94 FDRE r displaydriver/timer/xy/y_reg[2]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.610 8.590 displaydriver/timer/xy/clk100 + SLICE_X82Y94 r displaydriver/timer/xy/y_reg[2]/C + clock pessimism 0.559 9.149 + clock uncertainty -0.074 9.076 + SLICE_X82Y94 FDRE (Setup_fdre_C_R) -0.429 8.647 displaydriver/timer/xy/y_reg[2] + ------------------------------------------------------------------- + required time 8.647 + arrival time -2.763 + ------------------------------------------------------------------- + slack 5.884 + +Slack (MET) : 5.884ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[3]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.578ns (logic 0.890ns (24.873%) route 2.688ns (75.127%)) + Logic Levels: 3 (LUT6=3) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.410ns = ( 8.590 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.518 -0.298 f displaydriver/timer/xy/x_reg[5]/Q + net (fo=71, routed) 1.267 0.969 displaydriver/timer/xy/Q[1] + SLICE_X83Y93 LUT6 (Prop_lut6_I3_O) 0.124 1.093 r displaydriver/timer/xy/y[9]_i_6/O + net (fo=1, routed) 0.299 1.392 displaydriver/timer/xy/n_0_y[9]_i_6 + SLICE_X82Y94 LUT6 (Prop_lut6_I5_O) 0.124 1.516 r displaydriver/timer/xy/y[9]_i_4/O + net (fo=1, routed) 0.387 1.903 displaydriver/timer/xy/n_0_y[9]_i_4 + SLICE_X81Y94 LUT6 (Prop_lut6_I5_O) 0.124 2.027 r displaydriver/timer/xy/y[9]_i_1/O + net (fo=10, routed) 0.736 2.763 displaydriver/timer/xy/n_0_y[9]_i_1 + SLICE_X82Y94 FDRE r displaydriver/timer/xy/y_reg[3]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.610 8.590 displaydriver/timer/xy/clk100 + SLICE_X82Y94 r displaydriver/timer/xy/y_reg[3]/C + clock pessimism 0.559 9.149 + clock uncertainty -0.074 9.076 + SLICE_X82Y94 FDRE (Setup_fdre_C_R) -0.429 8.647 displaydriver/timer/xy/y_reg[3] + ------------------------------------------------------------------- + required time 8.647 + arrival time -2.763 + ------------------------------------------------------------------- + slack 5.884 + +Slack (MET) : 5.884ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[4]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.578ns (logic 0.890ns (24.873%) route 2.688ns (75.127%)) + Logic Levels: 3 (LUT6=3) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.410ns = ( 8.590 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.518 -0.298 f displaydriver/timer/xy/x_reg[5]/Q + net (fo=71, routed) 1.267 0.969 displaydriver/timer/xy/Q[1] + SLICE_X83Y93 LUT6 (Prop_lut6_I3_O) 0.124 1.093 r displaydriver/timer/xy/y[9]_i_6/O + net (fo=1, routed) 0.299 1.392 displaydriver/timer/xy/n_0_y[9]_i_6 + SLICE_X82Y94 LUT6 (Prop_lut6_I5_O) 0.124 1.516 r displaydriver/timer/xy/y[9]_i_4/O + net (fo=1, routed) 0.387 1.903 displaydriver/timer/xy/n_0_y[9]_i_4 + SLICE_X81Y94 LUT6 (Prop_lut6_I5_O) 0.124 2.027 r displaydriver/timer/xy/y[9]_i_1/O + net (fo=10, routed) 0.736 2.763 displaydriver/timer/xy/n_0_y[9]_i_1 + SLICE_X82Y94 FDRE r displaydriver/timer/xy/y_reg[4]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.610 8.590 displaydriver/timer/xy/clk100 + SLICE_X82Y94 r displaydriver/timer/xy/y_reg[4]/C + clock pessimism 0.559 9.149 + clock uncertainty -0.074 9.076 + SLICE_X82Y94 FDRE (Setup_fdre_C_R) -0.429 8.647 displaydriver/timer/xy/y_reg[4] + ------------------------------------------------------------------- + required time 8.647 + arrival time -2.763 + ------------------------------------------------------------------- + slack 5.884 + +Slack (MET) : 5.889ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[0]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.574ns (logic 0.890ns (24.903%) route 2.684ns (75.097%)) + Logic Levels: 3 (LUT6=3) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.410ns = ( 8.590 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.518 -0.298 f displaydriver/timer/xy/x_reg[5]/Q + net (fo=71, routed) 1.267 0.969 displaydriver/timer/xy/Q[1] + SLICE_X83Y93 LUT6 (Prop_lut6_I3_O) 0.124 1.093 r displaydriver/timer/xy/y[9]_i_6/O + net (fo=1, routed) 0.299 1.392 displaydriver/timer/xy/n_0_y[9]_i_6 + SLICE_X82Y94 LUT6 (Prop_lut6_I5_O) 0.124 1.516 r displaydriver/timer/xy/y[9]_i_4/O + net (fo=1, routed) 0.387 1.903 displaydriver/timer/xy/n_0_y[9]_i_4 + SLICE_X81Y94 LUT6 (Prop_lut6_I5_O) 0.124 2.027 r displaydriver/timer/xy/y[9]_i_1/O + net (fo=10, routed) 0.731 2.758 displaydriver/timer/xy/n_0_y[9]_i_1 + SLICE_X83Y94 FDRE r displaydriver/timer/xy/y_reg[0]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.610 8.590 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[0]/C + clock pessimism 0.559 9.149 + clock uncertainty -0.074 9.076 + SLICE_X83Y94 FDRE (Setup_fdre_C_R) -0.429 8.647 displaydriver/timer/xy/y_reg[0] + ------------------------------------------------------------------- + required time 8.647 + arrival time -2.758 + ------------------------------------------------------------------- + slack 5.889 + +Slack (MET) : 5.889ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[1]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.574ns (logic 0.890ns (24.903%) route 2.684ns (75.097%)) + Logic Levels: 3 (LUT6=3) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.410ns = ( 8.590 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.518 -0.298 f displaydriver/timer/xy/x_reg[5]/Q + net (fo=71, routed) 1.267 0.969 displaydriver/timer/xy/Q[1] + SLICE_X83Y93 LUT6 (Prop_lut6_I3_O) 0.124 1.093 r displaydriver/timer/xy/y[9]_i_6/O + net (fo=1, routed) 0.299 1.392 displaydriver/timer/xy/n_0_y[9]_i_6 + SLICE_X82Y94 LUT6 (Prop_lut6_I5_O) 0.124 1.516 r displaydriver/timer/xy/y[9]_i_4/O + net (fo=1, routed) 0.387 1.903 displaydriver/timer/xy/n_0_y[9]_i_4 + SLICE_X81Y94 LUT6 (Prop_lut6_I5_O) 0.124 2.027 r displaydriver/timer/xy/y[9]_i_1/O + net (fo=10, routed) 0.731 2.758 displaydriver/timer/xy/n_0_y[9]_i_1 + SLICE_X83Y94 FDRE r displaydriver/timer/xy/y_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.610 8.590 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[1]/C + clock pessimism 0.559 9.149 + clock uncertainty -0.074 9.076 + SLICE_X83Y94 FDRE (Setup_fdre_C_R) -0.429 8.647 displaydriver/timer/xy/y_reg[1] + ------------------------------------------------------------------- + required time 8.647 + arrival time -2.758 + ------------------------------------------------------------------- + slack 5.889 + +Slack (MET) : 5.889ns (required time - arrival time) + Source: displaydriver/timer/xy/x_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[5]/R + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout0 rise@10.000ns - clkout0 rise@0.000ns) + Data Path Delay: 3.574ns (logic 0.890ns (24.903%) route 2.684ns (75.097%)) + Logic Levels: 3 (LUT6=3) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.410ns = ( 8.590 - 10.000 ) + Source Clock Delay (SCD): -0.816ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.129ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 -4.111 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.475 -2.636 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf100/O + net (fo=26, routed) 1.724 -0.816 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.518 -0.298 f displaydriver/timer/xy/x_reg[5]/Q + net (fo=71, routed) 1.267 0.969 displaydriver/timer/xy/Q[1] + SLICE_X83Y93 LUT6 (Prop_lut6_I3_O) 0.124 1.093 r displaydriver/timer/xy/y[9]_i_6/O + net (fo=1, routed) 0.299 1.392 displaydriver/timer/xy/n_0_y[9]_i_6 + SLICE_X82Y94 LUT6 (Prop_lut6_I5_O) 0.124 1.516 r displaydriver/timer/xy/y[9]_i_4/O + net (fo=1, routed) 0.387 1.903 displaydriver/timer/xy/n_0_y[9]_i_4 + SLICE_X81Y94 LUT6 (Prop_lut6_I5_O) 0.124 2.027 r displaydriver/timer/xy/y[9]_i_1/O + net (fo=10, routed) 0.731 2.758 displaydriver/timer/xy/n_0_y[9]_i_1 + SLICE_X83Y94 FDRE r displaydriver/timer/xy/y_reg[5]/R + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 10.000 10.000 r + E3 0.000 10.000 r clk + net (fo=0) 0.000 10.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 11.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 12.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.087 5.486 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.402 6.888 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 6.979 r clkdv/buf100/O + net (fo=26, routed) 1.610 8.590 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[5]/C + clock pessimism 0.559 9.149 + clock uncertainty -0.074 9.076 + SLICE_X83Y94 FDRE (Setup_fdre_C_R) -0.429 8.647 displaydriver/timer/xy/y_reg[5] + ------------------------------------------------------------------- + required time 8.647 + arrival time -2.758 + ------------------------------------------------------------------- + slack 5.889 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.192ns (arrival time - required time) + Source: displaydriver/timer/xy/x_reg[1]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/x_reg[5]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.186ns (52.635%) route 0.167ns (47.365%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns + Source Clock Delay (SCD): -0.564ns + Clock Pessimism Removal (CPR): -0.275ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.600 -0.564 displaydriver/timer/xy/clk100 + SLICE_X79Y96 r displaydriver/timer/xy/x_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.423 r displaydriver/timer/xy/x_reg[1]/Q + net (fo=9, routed) 0.167 -0.256 displaydriver/timer/xy/bmem_addr[1] + SLICE_X80Y96 LUT6 (Prop_lut6_I3_O) 0.045 -0.211 r displaydriver/timer/xy/x[5]_i_1/O + net (fo=1, routed) 0.000 -0.211 displaydriver/timer/xy/sel0[5] + SLICE_X80Y96 FDRE r displaydriver/timer/xy/x_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.874 -0.799 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]/C + clock pessimism 0.275 -0.524 + SLICE_X80Y96 FDRE (Hold_fdre_C_D) 0.121 -0.403 displaydriver/timer/xy/x_reg[5] + ------------------------------------------------------------------- + required time 0.403 + arrival time -0.211 + ------------------------------------------------------------------- + slack 0.192 + +Slack (MET) : 0.211ns (arrival time - required time) + Source: displaydriver/timer/xy/y_reg[0]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[3]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.331ns (logic 0.189ns (57.035%) route 0.142ns (42.965%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.795ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.250ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.606 -0.558 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y94 FDRE (Prop_fdre_C_Q) 0.141 -0.417 r displaydriver/timer/xy/y_reg[0]/Q + net (fo=8, routed) 0.142 -0.275 displaydriver/timer/xy/bmem_addr[4] + SLICE_X82Y94 LUT4 (Prop_lut4_I1_O) 0.048 -0.227 r displaydriver/timer/xy/y[3]_i_1/O + net (fo=1, routed) 0.000 -0.227 displaydriver/timer/xy/n_0_y[3]_i_1 + SLICE_X82Y94 FDRE r displaydriver/timer/xy/y_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.878 -0.795 displaydriver/timer/xy/clk100 + SLICE_X82Y94 r displaydriver/timer/xy/y_reg[3]/C + clock pessimism 0.250 -0.545 + SLICE_X82Y94 FDRE (Hold_fdre_C_D) 0.107 -0.438 displaydriver/timer/xy/y_reg[3] + ------------------------------------------------------------------- + required time 0.438 + arrival time -0.227 + ------------------------------------------------------------------- + slack 0.211 + +Slack (MET) : 0.213ns (arrival time - required time) + Source: displaydriver/timer/xy/y_reg[2]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[5]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.318ns (logic 0.186ns (58.467%) route 0.132ns (41.533%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.795ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.250ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.606 -0.558 displaydriver/timer/xy/clk100 + SLICE_X82Y94 r displaydriver/timer/xy/y_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X82Y94 FDRE (Prop_fdre_C_Q) 0.141 -0.417 r displaydriver/timer/xy/y_reg[2]/Q + net (fo=7, routed) 0.132 -0.285 displaydriver/timer/xy/bmem_addr[6] + SLICE_X83Y94 LUT6 (Prop_lut6_I1_O) 0.045 -0.240 r displaydriver/timer/xy/y[5]_i_1/O + net (fo=1, routed) 0.000 -0.240 displaydriver/timer/xy/n_0_y[5]_i_1 + SLICE_X83Y94 FDRE r displaydriver/timer/xy/y_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.878 -0.795 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[5]/C + clock pessimism 0.250 -0.545 + SLICE_X83Y94 FDRE (Hold_fdre_C_D) 0.092 -0.453 displaydriver/timer/xy/y_reg[5] + ------------------------------------------------------------------- + required time 0.453 + arrival time -0.240 + ------------------------------------------------------------------- + slack 0.213 + +Slack (MET) : 0.216ns (arrival time - required time) + Source: displaydriver/timer/xy/y_reg[0]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[4]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.190ns (56.993%) route 0.143ns (43.007%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.795ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.250ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.606 -0.558 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y94 FDRE (Prop_fdre_C_Q) 0.141 -0.417 r displaydriver/timer/xy/y_reg[0]/Q + net (fo=8, routed) 0.143 -0.274 displaydriver/timer/xy/bmem_addr[4] + SLICE_X82Y94 LUT5 (Prop_lut5_I2_O) 0.049 -0.225 r displaydriver/timer/xy/y[4]_i_1/O + net (fo=1, routed) 0.000 -0.225 displaydriver/timer/xy/n_0_y[4]_i_1 + SLICE_X82Y94 FDRE r displaydriver/timer/xy/y_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.878 -0.795 displaydriver/timer/xy/clk100 + SLICE_X82Y94 r displaydriver/timer/xy/y_reg[4]/C + clock pessimism 0.250 -0.545 + SLICE_X82Y94 FDRE (Hold_fdre_C_D) 0.104 -0.441 displaydriver/timer/xy/y_reg[4] + ------------------------------------------------------------------- + required time 0.441 + arrival time -0.225 + ------------------------------------------------------------------- + slack 0.216 + +Slack (MET) : 0.224ns (arrival time - required time) + Source: displaydriver/timer/xy/y_reg[0]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[2]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.328ns (logic 0.186ns (56.642%) route 0.142ns (43.358%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.795ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.250ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.606 -0.558 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y94 FDRE (Prop_fdre_C_Q) 0.141 -0.417 r displaydriver/timer/xy/y_reg[0]/Q + net (fo=8, routed) 0.142 -0.275 displaydriver/timer/xy/bmem_addr[4] + SLICE_X82Y94 LUT3 (Prop_lut3_I1_O) 0.045 -0.230 r displaydriver/timer/xy/y[2]_i_1/O + net (fo=1, routed) 0.000 -0.230 displaydriver/timer/xy/n_0_y[2]_i_1 + SLICE_X82Y94 FDRE r displaydriver/timer/xy/y_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.878 -0.795 displaydriver/timer/xy/clk100 + SLICE_X82Y94 r displaydriver/timer/xy/y_reg[2]/C + clock pessimism 0.250 -0.545 + SLICE_X82Y94 FDRE (Hold_fdre_C_D) 0.091 -0.454 displaydriver/timer/xy/y_reg[2] + ------------------------------------------------------------------- + required time 0.454 + arrival time -0.230 + ------------------------------------------------------------------- + slack 0.224 + +Slack (MET) : 0.231ns (arrival time - required time) + Source: displaydriver/timer/xy/x_reg[3]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/x_reg[5]_rep/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.351ns (logic 0.246ns (70.151%) route 0.105ns (29.849%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns + Source Clock Delay (SCD): -0.562ns + Clock Pessimism Removal (CPR): -0.237ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.602 -0.562 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.148 -0.414 r displaydriver/timer/xy/x_reg[3]/Q + net (fo=7, routed) 0.105 -0.310 displaydriver/timer/xy/bmem_addr[3] + SLICE_X80Y96 LUT6 (Prop_lut6_I4_O) 0.098 -0.212 r displaydriver/timer/xy/x[5]_rep_i_1/O + net (fo=1, routed) 0.000 -0.212 displaydriver/timer/xy/n_0_x[5]_rep_i_1 + SLICE_X80Y96 FDRE r displaydriver/timer/xy/x_reg[5]_rep/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.874 -0.799 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[5]_rep/C + clock pessimism 0.237 -0.562 + SLICE_X80Y96 FDRE (Hold_fdre_C_D) 0.120 -0.442 displaydriver/timer/xy/x_reg[5]_rep + ------------------------------------------------------------------- + required time 0.442 + arrival time -0.212 + ------------------------------------------------------------------- + slack 0.231 + +Slack (MET) : 0.232ns (arrival time - required time) + Source: displaydriver/timer/xy/y_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/y_reg[9]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.340ns (logic 0.186ns (54.772%) route 0.154ns (45.228%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.795ns + Source Clock Delay (SCD): -0.558ns + Clock Pessimism Removal (CPR): -0.253ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.606 -0.558 displaydriver/timer/xy/clk100 + SLICE_X83Y94 r displaydriver/timer/xy/y_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y94 FDRE (Prop_fdre_C_Q) 0.141 -0.417 r displaydriver/timer/xy/y_reg[5]/Q + net (fo=9, routed) 0.154 -0.264 displaydriver/timer/xy/O1[1] + SLICE_X83Y93 LUT6 (Prop_lut6_I1_O) 0.045 -0.219 r displaydriver/timer/xy/y[9]_i_2/O + net (fo=1, routed) 0.000 -0.219 displaydriver/timer/xy/n_0_y[9]_i_2 + SLICE_X83Y93 FDRE r displaydriver/timer/xy/y_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.878 -0.795 displaydriver/timer/xy/clk100 + SLICE_X83Y93 r displaydriver/timer/xy/y_reg[9]/C + clock pessimism 0.253 -0.542 + SLICE_X83Y93 FDRE (Hold_fdre_C_D) 0.092 -0.450 displaydriver/timer/xy/y_reg[9] + ------------------------------------------------------------------- + required time 0.450 + arrival time -0.219 + ------------------------------------------------------------------- + slack 0.232 + +Slack (MET) : 0.242ns (arrival time - required time) + Source: displaydriver/timer/xy/x_reg[0]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/xy/x_reg[5]_rep__0/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.370ns (logic 0.209ns (56.465%) route 0.161ns (43.535%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.801ns + Source Clock Delay (SCD): -0.562ns + Clock Pessimism Removal (CPR): -0.275ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.602 -0.562 displaydriver/timer/xy/clk100 + SLICE_X80Y96 r displaydriver/timer/xy/x_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X80Y96 FDRE (Prop_fdre_C_Q) 0.164 -0.398 r displaydriver/timer/xy/x_reg[0]/Q + net (fo=10, routed) 0.161 -0.237 displaydriver/timer/xy/bmem_addr[0] + SLICE_X79Y96 LUT6 (Prop_lut6_I2_O) 0.045 -0.192 r displaydriver/timer/xy/x[5]_rep_i_1__0/O + net (fo=1, routed) 0.000 -0.192 displaydriver/timer/xy/n_0_x[5]_rep_i_1__0 + SLICE_X79Y96 FDRE r displaydriver/timer/xy/x_reg[5]_rep__0/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.872 -0.801 displaydriver/timer/xy/clk100 + SLICE_X79Y96 r displaydriver/timer/xy/x_reg[5]_rep__0/C + clock pessimism 0.275 -0.526 + SLICE_X79Y96 FDRE (Hold_fdre_C_D) 0.092 -0.434 displaydriver/timer/xy/x_reg[5]_rep__0 + ------------------------------------------------------------------- + required time 0.434 + arrival time -0.192 + ------------------------------------------------------------------- + slack 0.242 + +Slack (MET) : 0.243ns (arrival time - required time) + Source: displaydriver/timer/clk_count_reg[0]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/clk_count_reg[1]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.350ns (logic 0.183ns (52.285%) route 0.167ns (47.715%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.800ns + Source Clock Delay (SCD): -0.563ns + Clock Pessimism Removal (CPR): -0.237ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.601 -0.563 displaydriver/timer/clk100 + SLICE_X79Y97 r displaydriver/timer/clk_count_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y97 FDRE (Prop_fdre_C_Q) 0.141 -0.422 r displaydriver/timer/clk_count_reg[0]/Q + net (fo=4, routed) 0.167 -0.255 displaydriver/timer/clk_count[0] + SLICE_X79Y97 LUT2 (Prop_lut2_I0_O) 0.042 -0.213 r displaydriver/timer/clk_count[1]_i_1/O + net (fo=1, routed) 0.000 -0.213 displaydriver/timer/p_0_in[1] + SLICE_X79Y97 FDRE r displaydriver/timer/clk_count_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.873 -0.800 displaydriver/timer/clk100 + SLICE_X79Y97 r displaydriver/timer/clk_count_reg[1]/C + clock pessimism 0.237 -0.563 + SLICE_X79Y97 FDRE (Hold_fdre_C_D) 0.107 -0.456 displaydriver/timer/clk_count_reg[1] + ------------------------------------------------------------------- + required time 0.456 + arrival time -0.213 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.262ns (arrival time - required time) + Source: displaydriver/timer/clk_count_reg[0]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: displaydriver/timer/clk_count_reg[0]/D + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Path Group: clkout0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout0 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.186ns (52.691%) route 0.167ns (47.309%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.800ns + Source Clock Delay (SCD): -0.563ns + Clock Pessimism Removal (CPR): -0.237ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.413 -1.190 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf100/O + net (fo=26, routed) 0.601 -0.563 displaydriver/timer/clk100 + SLICE_X79Y97 r displaydriver/timer/clk_count_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X79Y97 FDRE (Prop_fdre_C_Q) 0.141 -0.422 f displaydriver/timer/clk_count_reg[0]/Q + net (fo=4, routed) 0.167 -0.255 displaydriver/timer/clk_count[0] + SLICE_X79Y97 LUT1 (Prop_lut1_I0_O) 0.045 -0.210 r displaydriver/timer/clk_count[0]_i_1/O + net (fo=1, routed) 0.000 -0.210 displaydriver/timer/p_0_in[0] + SLICE_X79Y97 FDRE r displaydriver/timer/clk_count_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.067 -2.149 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.448 -1.702 clkdv/clkout0 + BUFGCTRL_X0Y17 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf100/O + net (fo=26, routed) 0.873 -0.800 displaydriver/timer/clk100 + SLICE_X79Y97 r displaydriver/timer/clk_count_reg[0]/C + clock pessimism 0.237 -0.563 + SLICE_X79Y97 FDRE (Hold_fdre_C_D) 0.091 -0.472 displaydriver/timer/clk_count_reg[0] + ------------------------------------------------------------------- + required time 0.472 + arrival time -0.210 + ------------------------------------------------------------------- + slack 0.262 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkout0 +Waveform: { 0 5 } +Period: 10.000 +Sources: { clkdv/mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required Actual Slack Location Pin +Min Period n/a BUFGCTRL/I0 n/a 2.155 10.000 7.845 BUFGCTRL_X0Y17 clkdv/buf100/I0 +Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT0 +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X54Y101 clkdv/start_cnt_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X54Y101 clkdv/start_cnt_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X54Y101 clkdv/start_cnt_reg[2]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X79Y97 displaydriver/timer/clk_count_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X79Y97 displaydriver/timer/clk_count_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X80Y96 displaydriver/timer/xy/x_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X79Y96 displaydriver/timer/xy/x_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X79Y96 displaydriver/timer/xy/x_reg[2]/C +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT0 +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[0]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[1]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[2]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y97 displaydriver/timer/clk_count_reg[0]/C +Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y97 displaydriver/timer/clk_count_reg[0]/C +Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y97 displaydriver/timer/clk_count_reg[1]/C +Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y97 displaydriver/timer/clk_count_reg[1]/C +Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X80Y96 displaydriver/timer/xy/x_reg[0]/C +Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y96 displaydriver/timer/xy/x_reg[1]/C +Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y96 displaydriver/timer/xy/x_reg[2]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[0]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[1]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[1]/C +High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[2]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X54Y101 clkdv/start_cnt_reg[2]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y96 displaydriver/timer/xy/x_reg[1]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y96 displaydriver/timer/xy/x_reg[2]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y96 displaydriver/timer/xy/x_reg[4]/C +High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X79Y96 displaydriver/timer/xy/x_reg[4]_rep/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkout1 + To Clock: clkout1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkout1 +Waveform: { 0 10 } +Period: 20.000 +Sources: { clkdv/mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required Actual Slack Location Pin +Min Period n/a MMCME2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT1 +Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 20.000 193.360 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkout2 + To Clock: clkout2 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 38.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkout2 +Waveform: { 0 20 } +Period: 40.000 +Sources: { clkdv/mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required Actual Slack Location Pin +Min Period n/a MMCME2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT2 +Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT2 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkout3 + To Clock: clkout3 + +Setup : 0 Failing Endpoints, Worst Slack 52.402ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 38.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 52.402ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 27.284ns (logic 3.224ns (11.817%) route 24.060ns (88.183%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.432ns = ( 78.568 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 4.728 21.964 io/smem/mem_reg_512_639_4_4/A0 + SLICE_X66Y94 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 22.088 r io/smem/mem_reg_512_639_4_4/SP.LOW/O + net (fo=1, routed) 0.000 22.088 io/smem/mem_reg_512_639_4_4/SPO0 + SLICE_X66Y94 MUXF7 (Prop_muxf7_I0_O) 0.241 22.329 r io/smem/mem_reg_512_639_4_4/F7.SP/O + net (fo=1, routed) 0.905 23.235 mips/dp/rf/I26 + SLICE_X72Y93 LUT4 (Prop_lut4_I3_O) 0.298 23.533 r mips/dp/rf/reg_r1_0_31_0_5_i_109/O + net (fo=1, routed) 0.790 24.323 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_109 + SLICE_X72Y90 LUT6 (Prop_lut6_I1_O) 0.124 24.447 r mips/dp/rf/reg_r1_0_31_0_5_i_47/O + net (fo=1, routed) 1.026 25.473 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_47 + SLICE_X77Y84 LUT6 (Prop_lut6_I1_O) 0.124 25.597 r mips/dp/rf/reg_r1_0_31_0_5_i_7/O + net (fo=2, routed) 0.851 26.448 mips/dp/rf/rf_reg_r2_0_31_0_5/DIC0 + SLICE_X78Y78 RAMD32 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.588 78.568 mips/dp/rf/rf_reg_r2_0_31_0_5/WCLK + SLICE_X78Y78 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC/CLK + clock pessimism 0.559 79.127 + clock uncertainty -0.102 79.025 + SLICE_X78Y78 RAMD32 (Setup_ramd32_CLK_I) + -0.175 78.850 mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC + ------------------------------------------------------------------- + required time 78.850 + arrival time -26.448 + ------------------------------------------------------------------- + slack 52.402 + +Slack (MET) : 52.515ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r1_0_31_0_5/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 27.116ns (logic 3.224ns (11.890%) route 23.892ns (88.110%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.434ns = ( 78.566 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 4.797 22.033 io/smem/mem_reg_512_639_3_3/A0 + SLICE_X70Y94 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 22.157 r io/smem/mem_reg_512_639_3_3/SP.LOW/O + net (fo=1, routed) 0.000 22.157 io/smem/mem_reg_512_639_3_3/SPO0 + SLICE_X70Y94 MUXF7 (Prop_muxf7_I0_O) 0.241 22.398 r io/smem/mem_reg_512_639_3_3/F7.SP/O + net (fo=1, routed) 0.671 23.069 mips/dp/rf/I22 + SLICE_X72Y92 LUT4 (Prop_lut4_I3_O) 0.298 23.367 r mips/dp/rf/reg_r1_0_31_0_5_i_94/O + net (fo=1, routed) 1.082 24.449 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_94 + SLICE_X77Y90 LUT6 (Prop_lut6_I1_O) 0.124 24.573 r mips/dp/rf/reg_r1_0_31_0_5_i_35/O + net (fo=1, routed) 0.895 25.468 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_35 + SLICE_X79Y86 LUT6 (Prop_lut6_I1_O) 0.124 25.592 r mips/dp/rf/reg_r1_0_31_0_5_i_4/O + net (fo=2, routed) 0.689 26.280 mips/dp/rf/rf_reg_r1_0_31_0_5/DIB1 + SLICE_X78Y77 RAMD32 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.586 78.566 mips/dp/rf/rf_reg_r1_0_31_0_5/WCLK + SLICE_X78Y77 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMB_D1/CLK + clock pessimism 0.559 79.125 + clock uncertainty -0.102 79.023 + SLICE_X78Y77 RAMD32 (Setup_ramd32_CLK_I) + -0.228 78.795 mips/dp/rf/rf_reg_r1_0_31_0_5/RAMB_D1 + ------------------------------------------------------------------- + required time 78.795 + arrival time -26.280 + ------------------------------------------------------------------- + slack 52.515 + +Slack (MET) : 52.541ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 27.143ns (logic 3.224ns (11.878%) route 23.919ns (88.122%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.434ns = ( 78.566 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 4.728 21.964 io/smem/mem_reg_512_639_4_4/A0 + SLICE_X66Y94 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 22.088 r io/smem/mem_reg_512_639_4_4/SP.LOW/O + net (fo=1, routed) 0.000 22.088 io/smem/mem_reg_512_639_4_4/SPO0 + SLICE_X66Y94 MUXF7 (Prop_muxf7_I0_O) 0.241 22.329 r io/smem/mem_reg_512_639_4_4/F7.SP/O + net (fo=1, routed) 0.905 23.235 mips/dp/rf/I26 + SLICE_X72Y93 LUT4 (Prop_lut4_I3_O) 0.298 23.533 r mips/dp/rf/reg_r1_0_31_0_5_i_109/O + net (fo=1, routed) 0.790 24.323 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_109 + SLICE_X72Y90 LUT6 (Prop_lut6_I1_O) 0.124 24.447 r mips/dp/rf/reg_r1_0_31_0_5_i_47/O + net (fo=1, routed) 1.026 25.473 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_47 + SLICE_X77Y84 LUT6 (Prop_lut6_I1_O) 0.124 25.597 r mips/dp/rf/reg_r1_0_31_0_5_i_7/O + net (fo=2, routed) 0.710 26.307 mips/dp/rf/rf_reg_r1_0_31_0_5/DIC0 + SLICE_X78Y77 RAMD32 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.586 78.566 mips/dp/rf/rf_reg_r1_0_31_0_5/WCLK + SLICE_X78Y77 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC/CLK + clock pessimism 0.559 79.125 + clock uncertainty -0.102 79.023 + SLICE_X78Y77 RAMD32 (Setup_ramd32_CLK_I) + -0.175 78.848 mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC + ------------------------------------------------------------------- + required time 78.848 + arrival time -26.307 + ------------------------------------------------------------------- + slack 52.541 + +Slack (MET) : 52.657ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r2_0_31_0_5/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 26.976ns (logic 3.224ns (11.951%) route 23.752ns (88.049%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.432ns = ( 78.568 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 4.797 22.033 io/smem/mem_reg_512_639_3_3/A0 + SLICE_X70Y94 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 22.157 r io/smem/mem_reg_512_639_3_3/SP.LOW/O + net (fo=1, routed) 0.000 22.157 io/smem/mem_reg_512_639_3_3/SPO0 + SLICE_X70Y94 MUXF7 (Prop_muxf7_I0_O) 0.241 22.398 r io/smem/mem_reg_512_639_3_3/F7.SP/O + net (fo=1, routed) 0.671 23.069 mips/dp/rf/I22 + SLICE_X72Y92 LUT4 (Prop_lut4_I3_O) 0.298 23.367 r mips/dp/rf/reg_r1_0_31_0_5_i_94/O + net (fo=1, routed) 1.082 24.449 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_94 + SLICE_X77Y90 LUT6 (Prop_lut6_I1_O) 0.124 24.573 r mips/dp/rf/reg_r1_0_31_0_5_i_35/O + net (fo=1, routed) 0.895 25.468 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_35 + SLICE_X79Y86 LUT6 (Prop_lut6_I1_O) 0.124 25.592 r mips/dp/rf/reg_r1_0_31_0_5_i_4/O + net (fo=2, routed) 0.549 26.140 mips/dp/rf/rf_reg_r2_0_31_0_5/DIB1 + SLICE_X78Y78 RAMD32 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.588 78.568 mips/dp/rf/rf_reg_r2_0_31_0_5/WCLK + SLICE_X78Y78 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMB_D1/CLK + clock pessimism 0.559 79.127 + clock uncertainty -0.102 79.025 + SLICE_X78Y78 RAMD32 (Setup_ramd32_CLK_I) + -0.228 78.797 mips/dp/rf/rf_reg_r2_0_31_0_5/RAMB_D1 + ------------------------------------------------------------------- + required time 78.797 + arrival time -26.140 + ------------------------------------------------------------------- + slack 52.657 + +Slack (MET) : 53.196ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r2_0_31_0_5/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 26.407ns (logic 3.224ns (12.209%) route 23.183ns (87.791%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.432ns = ( 78.568 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 2.985 20.221 io/smem/mem_reg_896_1023_1_1/A0 + SLICE_X78Y93 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 20.345 r io/smem/mem_reg_896_1023_1_1/SP.LOW/O + net (fo=1, routed) 0.000 20.345 io/smem/mem_reg_896_1023_1_1/SPO0 + SLICE_X78Y93 MUXF7 (Prop_muxf7_I0_O) 0.241 20.586 r io/smem/mem_reg_896_1023_1_1/F7.SP/O + net (fo=1, routed) 0.965 21.551 mips/dp/rf/I45 + SLICE_X79Y91 LUT4 (Prop_lut4_I2_O) 0.298 21.849 r mips/dp/rf/reg_r1_0_31_0_5_i_73/O + net (fo=1, routed) 1.094 22.943 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_73 + SLICE_X81Y90 LUT6 (Prop_lut6_I0_O) 0.124 23.067 r mips/dp/rf/reg_r1_0_31_0_5_i_25/O + net (fo=1, routed) 1.236 24.303 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_25 + SLICE_X82Y82 LUT6 (Prop_lut6_I1_O) 0.124 24.427 r mips/dp/rf/reg_r1_0_31_0_5_i_2/O + net (fo=2, routed) 1.144 25.571 mips/dp/rf/rf_reg_r2_0_31_0_5/DIA1 + SLICE_X78Y78 RAMD32 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.588 78.568 mips/dp/rf/rf_reg_r2_0_31_0_5/WCLK + SLICE_X78Y78 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMA_D1/CLK + clock pessimism 0.559 79.127 + clock uncertainty -0.102 79.025 + SLICE_X78Y78 RAMD32 (Setup_ramd32_CLK_I) + -0.258 78.767 mips/dp/rf/rf_reg_r2_0_31_0_5/RAMA_D1 + ------------------------------------------------------------------- + required time 78.767 + arrival time -25.571 + ------------------------------------------------------------------- + slack 53.196 + +Slack (MET) : 53.394ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 26.216ns (logic 3.224ns (12.298%) route 22.992ns (87.702%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.434ns = ( 78.566 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 3.699 20.936 io/smem/mem_reg_512_639_5_5/A0 + SLICE_X74Y96 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 21.060 r io/smem/mem_reg_512_639_5_5/SP.LOW/O + net (fo=1, routed) 0.000 21.060 io/smem/mem_reg_512_639_5_5/SPO0 + SLICE_X74Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 21.301 r io/smem/mem_reg_512_639_5_5/F7.SP/O + net (fo=1, routed) 0.869 22.170 mips/dp/rf/I30 + SLICE_X77Y92 LUT4 (Prop_lut4_I3_O) 0.298 22.468 r mips/dp/rf/reg_r1_0_31_0_5_i_104/O + net (fo=1, routed) 0.810 23.277 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_104 + SLICE_X77Y90 LUT6 (Prop_lut6_I1_O) 0.124 23.401 r mips/dp/rf/reg_r1_0_31_0_5_i_43/O + net (fo=1, routed) 0.850 24.251 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_43 + SLICE_X77Y83 LUT6 (Prop_lut6_I1_O) 0.124 24.375 r mips/dp/rf/reg_r1_0_31_0_5_i_6/O + net (fo=2, routed) 1.005 25.380 mips/dp/rf/rf_reg_r1_0_31_0_5/DIC1 + SLICE_X78Y77 RAMD32 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.586 78.566 mips/dp/rf/rf_reg_r1_0_31_0_5/WCLK + SLICE_X78Y77 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC_D1/CLK + clock pessimism 0.559 79.125 + clock uncertainty -0.102 79.023 + SLICE_X78Y77 RAMD32 (Setup_ramd32_CLK_I) + -0.249 78.774 mips/dp/rf/rf_reg_r1_0_31_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 78.774 + arrival time -25.380 + ------------------------------------------------------------------- + slack 53.394 + +Slack (MET) : 53.538ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 26.063ns (logic 3.224ns (12.370%) route 22.839ns (87.630%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.434ns = ( 78.566 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 2.985 20.221 io/smem/mem_reg_896_1023_1_1/A0 + SLICE_X78Y93 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 20.345 r io/smem/mem_reg_896_1023_1_1/SP.LOW/O + net (fo=1, routed) 0.000 20.345 io/smem/mem_reg_896_1023_1_1/SPO0 + SLICE_X78Y93 MUXF7 (Prop_muxf7_I0_O) 0.241 20.586 r io/smem/mem_reg_896_1023_1_1/F7.SP/O + net (fo=1, routed) 0.965 21.551 mips/dp/rf/I45 + SLICE_X79Y91 LUT4 (Prop_lut4_I2_O) 0.298 21.849 r mips/dp/rf/reg_r1_0_31_0_5_i_73/O + net (fo=1, routed) 1.094 22.943 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_73 + SLICE_X81Y90 LUT6 (Prop_lut6_I0_O) 0.124 23.067 r mips/dp/rf/reg_r1_0_31_0_5_i_25/O + net (fo=1, routed) 1.236 24.303 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_25 + SLICE_X82Y82 LUT6 (Prop_lut6_I1_O) 0.124 24.427 r mips/dp/rf/reg_r1_0_31_0_5_i_2/O + net (fo=2, routed) 0.800 25.227 mips/dp/rf/rf_reg_r1_0_31_0_5/DIA1 + SLICE_X78Y77 RAMD32 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.586 78.566 mips/dp/rf/rf_reg_r1_0_31_0_5/WCLK + SLICE_X78Y77 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA_D1/CLK + clock pessimism 0.559 79.125 + clock uncertainty -0.102 79.023 + SLICE_X78Y77 RAMD32 (Setup_ramd32_CLK_I) + -0.258 78.765 mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA_D1 + ------------------------------------------------------------------- + required time 78.765 + arrival time -25.227 + ------------------------------------------------------------------- + slack 53.538 + +Slack (MET) : 53.673ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 25.939ns (logic 3.224ns (12.429%) route 22.715ns (87.571%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.432ns = ( 78.568 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 3.699 20.936 io/smem/mem_reg_512_639_5_5/A0 + SLICE_X74Y96 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 21.060 r io/smem/mem_reg_512_639_5_5/SP.LOW/O + net (fo=1, routed) 0.000 21.060 io/smem/mem_reg_512_639_5_5/SPO0 + SLICE_X74Y96 MUXF7 (Prop_muxf7_I0_O) 0.241 21.301 r io/smem/mem_reg_512_639_5_5/F7.SP/O + net (fo=1, routed) 0.869 22.170 mips/dp/rf/I30 + SLICE_X77Y92 LUT4 (Prop_lut4_I3_O) 0.298 22.468 r mips/dp/rf/reg_r1_0_31_0_5_i_104/O + net (fo=1, routed) 0.810 23.277 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_104 + SLICE_X77Y90 LUT6 (Prop_lut6_I1_O) 0.124 23.401 r mips/dp/rf/reg_r1_0_31_0_5_i_43/O + net (fo=1, routed) 0.850 24.251 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_43 + SLICE_X77Y83 LUT6 (Prop_lut6_I1_O) 0.124 24.375 r mips/dp/rf/reg_r1_0_31_0_5_i_6/O + net (fo=2, routed) 0.728 25.103 mips/dp/rf/rf_reg_r2_0_31_0_5/DIC1 + SLICE_X78Y78 RAMD32 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.588 78.568 mips/dp/rf/rf_reg_r2_0_31_0_5/WCLK + SLICE_X78Y78 r mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC_D1/CLK + clock pessimism 0.559 79.127 + clock uncertainty -0.102 79.025 + SLICE_X78Y78 RAMD32 (Setup_ramd32_CLK_I) + -0.249 78.776 mips/dp/rf/rf_reg_r2_0_31_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 78.776 + arrival time -25.104 + ------------------------------------------------------------------- + slack 53.673 + +Slack (MET) : 53.698ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r1_0_31_6_11/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 25.916ns (logic 3.460ns (13.351%) route 22.456ns (86.649%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.026ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.437ns = ( 78.563 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.575ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.629 17.078 mips/dp/rf/alu/compResult[0] + SLICE_X68Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.202 r mips/dp/rf/mem_reg_0_127_6_6_i_2/O + net (fo=112, routed) 2.337 19.539 io/smem/mem_reg_1024_1151_7_7/A0 + SLICE_X76Y83 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 19.663 r io/smem/mem_reg_1024_1151_7_7/SP.LOW/O + net (fo=1, routed) 0.000 19.663 io/smem/mem_reg_1024_1151_7_7/SPO0 + SLICE_X76Y83 MUXF7 (Prop_muxf7_I0_O) 0.241 19.904 r io/smem/mem_reg_1024_1151_7_7/F7.SP/O + net (fo=1, routed) 1.107 21.011 io/smem/n_1_mem_reg_1024_1151_7_7 + SLICE_X79Y83 LUT6 (Prop_lut6_I0_O) 0.298 21.309 r io/smem/rf_reg_r1_0_31_6_11_i_28/O + net (fo=1, routed) 0.875 22.184 mips/dp/rf/I78 + SLICE_X82Y83 LUT4 (Prop_lut4_I3_O) 0.152 22.336 r mips/dp/rf/reg_r1_0_31_6_11_i_9/O + net (fo=1, routed) 1.228 23.564 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_9 + SLICE_X73Y86 LUT6 (Prop_lut6_I2_O) 0.332 23.896 r mips/dp/rf/reg_r1_0_31_6_11_i_1/O + net (fo=2, routed) 1.184 25.080 mips/dp/rf/rf_reg_r1_0_31_6_11/DIA1 + SLICE_X76Y77 RAMD32 r mips/dp/rf/rf_reg_r1_0_31_6_11/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.583 78.563 mips/dp/rf/rf_reg_r1_0_31_6_11/WCLK + SLICE_X76Y77 r mips/dp/rf/rf_reg_r1_0_31_6_11/RAMA_D1/CLK + clock pessimism 0.575 79.138 + clock uncertainty -0.102 79.036 + SLICE_X76Y77 RAMD32 (Setup_ramd32_CLK_I) + -0.258 78.778 mips/dp/rf/rf_reg_r1_0_31_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 78.778 + arrival time -25.080 + ------------------------------------------------------------------- + slack 53.698 + +Slack (MET) : 53.993ns (required time - arrival time) + Source: mips/dp/pc_reg[5]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA/I + (rising edge-triggered cell RAMD32 clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 80.000ns (clkout3 rise@80.000ns - clkout3 rise@0.000ns) + Data Path Delay: 25.705ns (logic 3.224ns (12.542%) route 22.481ns (87.458%)) + Logic Levels: 16 (LUT3=2 LUT4=1 LUT5=3 LUT6=7 MUXF7=2 RAMD64E=1) + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.434ns = ( 78.566 - 80.000 ) + Source Clock Delay (SCD): -0.836ns + Clock Pessimism Removal (CPR): 0.559ns + Clock Uncertainty: 0.102ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 2.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -6.826 -4.111 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.475 -2.636 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.096 -2.540 r clkdv/buf12/O + net (fo=570, routed) 1.704 -0.836 mips/dp/clk12 + SLICE_X77Y79 r mips/dp/pc_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.380 r mips/dp/pc_reg[5]/Q + net (fo=60, routed) 2.911 2.531 mips/dp/rf/Q[5] + SLICE_X82Y78 LUT6 (Prop_lut6_I1_O) 0.124 2.655 r mips/dp/rf/reg_r1_0_31_0_5_i_66/O + net (fo=1, routed) 0.000 2.655 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_66 + SLICE_X82Y78 MUXF7 (Prop_muxf7_I0_O) 0.212 2.867 r mips/dp/rf/reg_r1_0_31_0_5_i_21/O + net (fo=23, routed) 1.273 4.140 mips/dp/rf/O14[20] + SLICE_X79Y80 LUT3 (Prop_lut3_I0_O) 0.299 4.439 r mips/dp/rf/mem_reg_0_127_0_0_i_124/O + net (fo=25, routed) 2.918 7.357 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_124 + SLICE_X77Y77 LUT6 (Prop_lut6_I1_O) 0.124 7.481 r mips/dp/rf/mem_reg_0_127_0_0_i_69/O + net (fo=70, routed) 1.263 8.745 mips/dp/rf/aluA[0] + SLICE_X68Y77 LUT3 (Prop_lut3_I2_O) 0.152 8.897 r mips/dp/rf/mem_reg_0_127_0_0_i_95/O + net (fo=3, routed) 0.971 9.868 mips/dp/rf/alu/AS/add/carry[1] + SLICE_X70Y76 LUT6 (Prop_lut6_I0_O) 0.326 10.194 r mips/dp/rf/mem_reg_0_127_0_0_i_81/O + net (fo=5, routed) 1.627 11.821 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_81 + SLICE_X78Y73 LUT5 (Prop_lut5_I2_O) 0.124 11.945 r mips/dp/rf/mem_reg_1024_1151_0_0_i_4/O + net (fo=10, routed) 1.822 13.767 mips/dp/rf/n_0_mem_reg_1024_1151_0_0_i_4 + SLICE_X70Y77 LUT5 (Prop_lut5_I2_O) 0.124 13.891 r mips/dp/rf/reg_r1_0_31_6_11_i_46/O + net (fo=17, routed) 1.642 15.533 mips/dp/rf/n_0_reg_r1_0_31_6_11_i_46 + SLICE_X66Y85 LUT6 (Prop_lut6_I2_O) 0.124 15.657 r mips/dp/rf/mem_reg_0_127_0_0_i_104/O + net (fo=3, routed) 0.668 16.325 mips/dp/rf/n_0_mem_reg_0_127_0_0_i_104 + SLICE_X67Y85 LUT6 (Prop_lut6_I0_O) 0.124 16.449 r mips/dp/rf/mem_reg_0_127_0_0_i_44/O + net (fo=4, routed) 0.663 17.112 mips/dp/rf/alu/compResult[0] + SLICE_X70Y80 LUT5 (Prop_lut5_I2_O) 0.124 17.236 r mips/dp/rf/mem_reg_0_127_0_0_i_9/O + net (fo=349, routed) 3.692 20.929 io/smem/mem_reg_896_1023_0_0/A0 + SLICE_X76Y94 RAMD64E (Prop_ramd64e_RADR0_O) + 0.124 21.053 r io/smem/mem_reg_896_1023_0_0/SP.LOW/O + net (fo=1, routed) 0.000 21.053 io/smem/mem_reg_896_1023_0_0/SPO0 + SLICE_X76Y94 MUXF7 (Prop_muxf7_I0_O) 0.241 21.294 r io/smem/mem_reg_896_1023_0_0/F7.SP/O + net (fo=1, routed) 0.501 21.795 mips/dp/rf/I41 + SLICE_X77Y94 LUT4 (Prop_lut4_I2_O) 0.298 22.093 r mips/dp/rf/reg_r1_0_31_0_5_i_88/O + net (fo=1, routed) 0.980 23.072 mips/dp/rf/n_0_reg_r1_0_31_0_5_i_88 + SLICE_X77Y90 LUT6 (Prop_lut6_I0_O) 0.124 23.196 r mips/dp/rf/reg_r1_0_31_0_5_i_31/O + net (fo=1, routed) 0.847 24.043 io/dmem/I24 + SLICE_X79Y85 LUT6 (Prop_lut6_I1_O) 0.124 24.167 r io/dmem/rf_reg_r1_0_31_0_5_i_3/O + net (fo=2, routed) 0.703 24.869 mips/dp/rf/rf_reg_r1_0_31_0_5/DIA0 + SLICE_X78Y77 RAMD32 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.091 76.979 r clkdv/buf12/O + net (fo=570, routed) 1.586 78.566 mips/dp/rf/rf_reg_r1_0_31_0_5/WCLK + SLICE_X78Y77 r mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA/CLK + clock pessimism 0.559 79.125 + clock uncertainty -0.102 79.023 + SLICE_X78Y77 RAMD32 (Setup_ramd32_CLK_I) + -0.161 78.862 mips/dp/rf/rf_reg_r1_0_31_0_5/RAMA + ------------------------------------------------------------------- + required time 78.862 + arrival time -24.869 + ------------------------------------------------------------------- + slack 53.993 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.094ns (arrival time - required time) + Source: rbouncer/count_reg[11]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: rbouncer/count_reg[12]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.356ns (76.581%) route 0.109ns (23.419%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): -0.595ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.569 -0.595 rbouncer/clk12 + SLICE_X69Y99 r rbouncer/count_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.454 r rbouncer/count_reg[11]/Q + net (fo=1, routed) 0.108 -0.346 rbouncer/n_0_count_reg[11] + SLICE_X69Y99 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.160 -0.186 r rbouncer/count_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.185 rbouncer/n_0_count_reg[8]_i_1 + SLICE_X69Y100 CARRY4 (Prop_carry4_CI_O[0]) + 0.055 -0.130 r rbouncer/count_reg[12]_i_1/O[0] + net (fo=1, routed) 0.000 -0.130 rbouncer/n_7_count_reg[12]_i_1 + SLICE_X69Y100 FDRE r rbouncer/count_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.835 -0.838 rbouncer/clk12 + SLICE_X69Y100 r rbouncer/count_reg[12]/C + clock pessimism 0.509 -0.329 + SLICE_X69Y100 FDRE (Hold_fdre_C_D) 0.105 -0.224 rbouncer/count_reg[12] + ------------------------------------------------------------------- + required time 0.224 + arrival time -0.130 + ------------------------------------------------------------------- + slack 0.094 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: rbouncer/count_reg[11]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: rbouncer/count_reg[14]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.366ns (77.074%) route 0.109ns (22.926%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): -0.595ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.569 -0.595 rbouncer/clk12 + SLICE_X69Y99 r rbouncer/count_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.454 r rbouncer/count_reg[11]/Q + net (fo=1, routed) 0.108 -0.346 rbouncer/n_0_count_reg[11] + SLICE_X69Y99 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.160 -0.186 r rbouncer/count_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.185 rbouncer/n_0_count_reg[8]_i_1 + SLICE_X69Y100 CARRY4 (Prop_carry4_CI_O[2]) + 0.065 -0.120 r rbouncer/count_reg[12]_i_1/O[2] + net (fo=1, routed) 0.000 -0.120 rbouncer/n_5_count_reg[12]_i_1 + SLICE_X69Y100 FDRE r rbouncer/count_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.835 -0.838 rbouncer/clk12 + SLICE_X69Y100 r rbouncer/count_reg[14]/C + clock pessimism 0.509 -0.329 + SLICE_X69Y100 FDRE (Hold_fdre_C_D) 0.105 -0.224 rbouncer/count_reg[14] + ------------------------------------------------------------------- + required time 0.224 + arrival time -0.120 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.107ns (arrival time - required time) + Source: io/kmem/timeout_reg[6]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: io/kmem/timeout_reg[8]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.478ns (logic 0.356ns (74.454%) route 0.122ns (25.546%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns + Source Clock Delay (SCD): -0.556ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.608 -0.556 io/kmem/clk12 + SLICE_X86Y99 r io/kmem/timeout_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.415 r io/kmem/timeout_reg[6]/Q + net (fo=1, routed) 0.121 -0.294 io/kmem/n_0_timeout_reg[6] + SLICE_X86Y99 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.160 -0.134 r io/kmem/timeout_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.133 io/kmem/n_0_timeout_reg[4]_i_1 + SLICE_X86Y100 CARRY4 (Prop_carry4_CI_O[0]) + 0.055 -0.078 r io/kmem/timeout_reg[8]_i_1/O[0] + net (fo=1, routed) 0.000 -0.078 io/kmem/n_7_timeout_reg[8]_i_1 + SLICE_X86Y100 FDRE r io/kmem/timeout_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.873 -0.799 io/kmem/clk12 + SLICE_X86Y100 r io/kmem/timeout_reg[8]/C + clock pessimism 0.509 -0.290 + SLICE_X86Y100 FDRE (Hold_fdre_C_D) 0.105 -0.185 io/kmem/timeout_reg[8] + ------------------------------------------------------------------- + required time 0.185 + arrival time -0.078 + ------------------------------------------------------------------- + slack 0.107 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: io/kmem/timeout_reg[6]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: io/kmem/timeout_reg[10]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.366ns (74.977%) route 0.122ns (25.023%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns + Source Clock Delay (SCD): -0.556ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.608 -0.556 io/kmem/clk12 + SLICE_X86Y99 r io/kmem/timeout_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.415 r io/kmem/timeout_reg[6]/Q + net (fo=1, routed) 0.121 -0.294 io/kmem/n_0_timeout_reg[6] + SLICE_X86Y99 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.160 -0.134 r io/kmem/timeout_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.133 io/kmem/n_0_timeout_reg[4]_i_1 + SLICE_X86Y100 CARRY4 (Prop_carry4_CI_O[2]) + 0.065 -0.068 r io/kmem/timeout_reg[8]_i_1/O[2] + net (fo=1, routed) 0.000 -0.068 io/kmem/n_5_timeout_reg[8]_i_1 + SLICE_X86Y100 FDRE r io/kmem/timeout_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.873 -0.799 io/kmem/clk12 + SLICE_X86Y100 r io/kmem/timeout_reg[10]/C + clock pessimism 0.509 -0.290 + SLICE_X86Y100 FDRE (Hold_fdre_C_D) 0.105 -0.185 io/kmem/timeout_reg[10] + ------------------------------------------------------------------- + required time 0.185 + arrival time -0.068 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.129ns (arrival time - required time) + Source: rbouncer/count_reg[11]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: rbouncer/count_reg[13]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.500ns (logic 0.391ns (78.221%) route 0.109ns (21.779%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): -0.595ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.569 -0.595 rbouncer/clk12 + SLICE_X69Y99 r rbouncer/count_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.454 r rbouncer/count_reg[11]/Q + net (fo=1, routed) 0.108 -0.346 rbouncer/n_0_count_reg[11] + SLICE_X69Y99 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.160 -0.186 r rbouncer/count_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.185 rbouncer/n_0_count_reg[8]_i_1 + SLICE_X69Y100 CARRY4 (Prop_carry4_CI_O[1]) + 0.090 -0.095 r rbouncer/count_reg[12]_i_1/O[1] + net (fo=1, routed) 0.000 -0.095 rbouncer/n_6_count_reg[12]_i_1 + SLICE_X69Y100 FDRE r rbouncer/count_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.835 -0.838 rbouncer/clk12 + SLICE_X69Y100 r rbouncer/count_reg[13]/C + clock pessimism 0.509 -0.329 + SLICE_X69Y100 FDRE (Hold_fdre_C_D) 0.105 -0.224 rbouncer/count_reg[13] + ------------------------------------------------------------------- + required time 0.224 + arrival time -0.095 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.129ns (arrival time - required time) + Source: rbouncer/count_reg[11]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: rbouncer/count_reg[15]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.500ns (logic 0.391ns (78.221%) route 0.109ns (21.779%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): -0.595ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.569 -0.595 rbouncer/clk12 + SLICE_X69Y99 r rbouncer/count_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.454 r rbouncer/count_reg[11]/Q + net (fo=1, routed) 0.108 -0.346 rbouncer/n_0_count_reg[11] + SLICE_X69Y99 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.160 -0.186 r rbouncer/count_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.185 rbouncer/n_0_count_reg[8]_i_1 + SLICE_X69Y100 CARRY4 (Prop_carry4_CI_O[3]) + 0.090 -0.095 r rbouncer/count_reg[12]_i_1/O[3] + net (fo=1, routed) 0.000 -0.095 rbouncer/n_4_count_reg[12]_i_1 + SLICE_X69Y100 FDRE r rbouncer/count_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.835 -0.838 rbouncer/clk12 + SLICE_X69Y100 r rbouncer/count_reg[15]/C + clock pessimism 0.509 -0.329 + SLICE_X69Y100 FDRE (Hold_fdre_C_D) 0.105 -0.224 rbouncer/count_reg[15] + ------------------------------------------------------------------- + required time 0.224 + arrival time -0.095 + ------------------------------------------------------------------- + slack 0.129 + +Slack (MET) : 0.133ns (arrival time - required time) + Source: rbouncer/count_reg[11]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: rbouncer/count_reg[16]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.504ns (logic 0.395ns (78.394%) route 0.109ns (21.606%)) + Logic Levels: 3 (CARRY4=3) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): -0.595ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.569 -0.595 rbouncer/clk12 + SLICE_X69Y99 r rbouncer/count_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.454 r rbouncer/count_reg[11]/Q + net (fo=1, routed) 0.108 -0.346 rbouncer/n_0_count_reg[11] + SLICE_X69Y99 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.160 -0.186 r rbouncer/count_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.185 rbouncer/n_0_count_reg[8]_i_1 + SLICE_X69Y100 CARRY4 (Prop_carry4_CI_CO[3]) + 0.039 -0.146 r rbouncer/count_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 -0.146 rbouncer/n_0_count_reg[12]_i_1 + SLICE_X69Y101 CARRY4 (Prop_carry4_CI_O[0]) + 0.055 -0.091 r rbouncer/count_reg[16]_i_1/O[0] + net (fo=1, routed) 0.000 -0.091 rbouncer/n_7_count_reg[16]_i_1 + SLICE_X69Y101 FDRE r rbouncer/count_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.835 -0.838 rbouncer/clk12 + SLICE_X69Y101 r rbouncer/count_reg[16]/C + clock pessimism 0.509 -0.329 + SLICE_X69Y101 FDRE (Hold_fdre_C_D) 0.105 -0.224 rbouncer/count_reg[16] + ------------------------------------------------------------------- + required time 0.224 + arrival time -0.091 + ------------------------------------------------------------------- + slack 0.133 + +Slack (MET) : 0.142ns (arrival time - required time) + Source: io/kmem/timeout_reg[6]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: io/kmem/timeout_reg[11]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.513ns (logic 0.391ns (76.196%) route 0.122ns (23.804%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns + Source Clock Delay (SCD): -0.556ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.608 -0.556 io/kmem/clk12 + SLICE_X86Y99 r io/kmem/timeout_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.415 r io/kmem/timeout_reg[6]/Q + net (fo=1, routed) 0.121 -0.294 io/kmem/n_0_timeout_reg[6] + SLICE_X86Y99 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.160 -0.134 r io/kmem/timeout_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.133 io/kmem/n_0_timeout_reg[4]_i_1 + SLICE_X86Y100 CARRY4 (Prop_carry4_CI_O[3]) + 0.090 -0.043 r io/kmem/timeout_reg[8]_i_1/O[3] + net (fo=1, routed) 0.000 -0.043 io/kmem/n_4_timeout_reg[8]_i_1 + SLICE_X86Y100 FDRE r io/kmem/timeout_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.873 -0.799 io/kmem/clk12 + SLICE_X86Y100 r io/kmem/timeout_reg[11]/C + clock pessimism 0.509 -0.290 + SLICE_X86Y100 FDRE (Hold_fdre_C_D) 0.105 -0.185 io/kmem/timeout_reg[11] + ------------------------------------------------------------------- + required time 0.185 + arrival time -0.043 + ------------------------------------------------------------------- + slack 0.142 + +Slack (MET) : 0.142ns (arrival time - required time) + Source: io/kmem/timeout_reg[6]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: io/kmem/timeout_reg[9]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.513ns (logic 0.391ns (76.196%) route 0.122ns (23.804%)) + Logic Levels: 2 (CARRY4=2) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.799ns + Source Clock Delay (SCD): -0.556ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.608 -0.556 io/kmem/clk12 + SLICE_X86Y99 r io/kmem/timeout_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X86Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.415 r io/kmem/timeout_reg[6]/Q + net (fo=1, routed) 0.121 -0.294 io/kmem/n_0_timeout_reg[6] + SLICE_X86Y99 CARRY4 (Prop_carry4_S[2]_CO[3]) + 0.160 -0.134 r io/kmem/timeout_reg[4]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.133 io/kmem/n_0_timeout_reg[4]_i_1 + SLICE_X86Y100 CARRY4 (Prop_carry4_CI_O[1]) + 0.090 -0.043 r io/kmem/timeout_reg[8]_i_1/O[1] + net (fo=1, routed) 0.000 -0.043 io/kmem/n_6_timeout_reg[8]_i_1 + SLICE_X86Y100 FDRE r io/kmem/timeout_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.873 -0.799 io/kmem/clk12 + SLICE_X86Y100 r io/kmem/timeout_reg[9]/C + clock pessimism 0.509 -0.290 + SLICE_X86Y100 FDRE (Hold_fdre_C_D) 0.105 -0.185 io/kmem/timeout_reg[9] + ------------------------------------------------------------------- + required time 0.185 + arrival time -0.043 + ------------------------------------------------------------------- + slack 0.142 + +Slack (MET) : 0.143ns (arrival time - required time) + Source: rbouncer/count_reg[11]/C + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Destination: rbouncer/count_reg[18]/D + (rising edge-triggered cell FDRE clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout3 rise@0.000ns) + Data Path Delay: 0.514ns (logic 0.405ns (78.814%) route 0.109ns (21.186%)) + Logic Levels: 3 (CARRY4=3) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): -0.595ns + Clock Pessimism Removal (CPR): -0.509ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -2.293 -1.603 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.413 -1.190 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.026 -1.164 r clkdv/buf12/O + net (fo=570, routed) 0.569 -0.595 rbouncer/clk12 + SLICE_X69Y99 r rbouncer/count_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y99 FDRE (Prop_fdre_C_Q) 0.141 -0.454 r rbouncer/count_reg[11]/Q + net (fo=1, routed) 0.108 -0.346 rbouncer/n_0_count_reg[11] + SLICE_X69Y99 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.160 -0.186 r rbouncer/count_reg[8]_i_1/CO[3] + net (fo=1, routed) 0.001 -0.185 rbouncer/n_0_count_reg[8]_i_1 + SLICE_X69Y100 CARRY4 (Prop_carry4_CI_CO[3]) + 0.039 -0.146 r rbouncer/count_reg[12]_i_1/CO[3] + net (fo=1, routed) 0.000 -0.146 rbouncer/n_0_count_reg[12]_i_1 + SLICE_X69Y101 CARRY4 (Prop_carry4_CI_O[2]) + 0.065 -0.081 r rbouncer/count_reg[16]_i_1/O[2] + net (fo=1, routed) 0.000 -0.081 rbouncer/n_5_count_reg[16]_i_1 + SLICE_X69Y101 FDRE r rbouncer/count_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 BUFGCTRL (Prop_bufgctrl_I0_O) + 0.029 -1.673 r clkdv/buf12/O + net (fo=570, routed) 0.835 -0.838 rbouncer/clk12 + SLICE_X69Y101 r rbouncer/count_reg[18]/C + clock pessimism 0.509 -0.329 + SLICE_X69Y101 FDRE (Hold_fdre_C_D) 0.105 -0.224 rbouncer/count_reg[18] + ------------------------------------------------------------------- + required time 0.224 + arrival time -0.081 + ------------------------------------------------------------------- + slack 0.143 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clkout3 +Waveform: { 0 40 } +Period: 80.000 +Sources: { clkdv/mmcm/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required Actual Slack Location Pin +Min Period n/a BUFGCTRL/I0 n/a 2.155 80.000 77.845 BUFGCTRL_X0Y16 clkdv/buf12/I0 +Min Period n/a MMCME2_ADV/CLKOUT3 n/a 1.249 80.000 78.751 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT3 +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y85 io/disp/counter_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y87 io/disp/counter_reg[10]/C +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y87 io/disp/counter_reg[11]/C +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y88 io/disp/counter_reg[12]/C +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y88 io/disp/counter_reg[13]/C +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y88 io/disp/counter_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y88 io/disp/counter_reg[15]/C +Min Period n/a FDRE/C n/a 1.000 80.000 79.000 SLICE_X86Y89 io/disp/counter_reg[16]/C +Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 80.000 133.360 MMCME2_ADV_X1Y2 clkdv/mmcm/CLKOUT3 +Low Pulse Width Slow RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X78Y79 io/smem/mem_reg_0_31_0_0__5/SP/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X78Y79 io/smem/mem_reg_0_31_0_0__6/SP/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X78Y88 io/smem/mem_reg_128_255_6_6/DP.HIGH/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X78Y88 io/smem/mem_reg_128_255_6_6/DP.LOW/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X78Y88 io/smem/mem_reg_128_255_6_6/SP.HIGH/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X78Y88 io/smem/mem_reg_128_255_6_6/SP.LOW/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X76Y82 io/smem/mem_reg_256_383_3_3/DP.HIGH/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X76Y82 io/smem/mem_reg_256_383_3_3/DP.LOW/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X76Y82 io/smem/mem_reg_256_383_3_3/SP.HIGH/CLK +Low Pulse Width Slow RAMD64E/CLK n/a 1.250 40.000 38.750 SLICE_X76Y82 io/smem/mem_reg_256_383_3_3/SP.LOW/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X78Y81 io/dmem/mem_reg_0_31_10_10/SP/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X78Y81 io/dmem/mem_reg_0_31_11_11/SP/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X78Y81 io/dmem/mem_reg_0_31_12_12/SP/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X78Y81 io/dmem/mem_reg_0_31_13_13/SP/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X70Y83 io/dmem/mem_reg_0_31_14_14/SP/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X70Y83 io/dmem/mem_reg_0_31_15_15/SP/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X70Y83 io/dmem/mem_reg_0_31_16_16/SP/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X70Y83 io/dmem/mem_reg_0_31_17_17/SP/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X70Y84 io/dmem/mem_reg_0_31_18_18/SP/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 40.000 38.750 SLICE_X70Y84 io/dmem/mem_reg_0_31_19_19/SP/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: clkout0 + To Clock: clkout3 + +Setup : 0 Failing Endpoints, Worst Slack 7.215ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.392ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 7.215ns (required time - arrival time) + Source: clkdv/start_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clkdv/buf12/CE0 + (rising edge-triggered cell BUFGCTRL clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 10.000ns (clkout3 rise@80.000ns - clkout0 rise@70.000ns) + Data Path Delay: 1.813ns (logic 0.773ns (42.648%) route 1.040ns (57.352%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.592ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -3.112ns = ( 76.888 - 80.000 ) + Source Clock Delay (SCD): -2.117ns = ( 67.882 - 70.000 ) + Clock Pessimism Removal (CPR): 0.402ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 70.000 70.000 r + E3 0.000 70.000 r clk + net (fo=0) 0.000 70.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.482 71.482 r clk_IBUF_inst/O + net (fo=1, routed) 1.233 72.715 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -6.826 65.889 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 1.994 67.883 clkdv/clkout0 + SLICE_X54Y101 r clkdv/start_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y101 FDRE (Prop_fdre_C_Q) 0.478 68.361 r clkdv/start_cnt_reg[2]/Q + net (fo=4, routed) 0.468 68.828 clkdv/p_0_in + SLICE_X54Y101 LUT2 (Prop_lut2_I0_O) 0.295 69.123 f clkdv/buf100_i_1/O + net (fo=4, routed) 0.572 69.695 clkdv/not_clock_enable + BUFGCTRL_X0Y16 BUFGCTRL r clkdv/buf12/CE0 (IS_INVERTED) + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 80.000 80.000 r + E3 0.000 80.000 r clk + net (fo=0) 0.000 80.000 clk + E3 IBUF (Prop_ibuf_I_O) 1.411 81.411 r clk_IBUF_inst/O + net (fo=1, routed) 1.162 82.573 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -7.087 75.486 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 1.402 76.888 clkdv/clkout3 + BUFGCTRL_X0Y16 r clkdv/buf12/I0 + clock pessimism 0.402 77.291 + clock uncertainty -0.222 77.069 + BUFGCTRL_X0Y16 BUFGCTRL (Setup_bufgctrl_I0_CE0) + -0.159 76.910 clkdv/buf12 + ------------------------------------------------------------------- + required time 76.910 + arrival time -69.695 + ------------------------------------------------------------------- + slack 7.215 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.392ns (arrival time - required time) + Source: clkdv/start_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by clkout0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clkdv/buf12/CE0 + (rising edge-triggered cell BUFGCTRL clocked by clkout3 {rise@0.000ns fall@40.000ns period=80.000ns}) + Path Group: clkout3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clkout3 rise@0.000ns - clkout0 rise@0.000ns) + Data Path Delay: 0.635ns (logic 0.246ns (38.770%) route 0.389ns (61.230%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.138ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.702ns + Source Clock Delay (SCD): -1.017ns + Clock Pessimism Removal (CPR): -0.547ns + Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.192ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clkout0 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r clk_IBUF_inst/O + net (fo=1, routed) 0.440 0.690 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.293 -1.603 r clkdv/mmcm/CLKOUT0 + net (fo=4, routed) 0.586 -1.017 clkdv/clkout0 + SLICE_X54Y101 r clkdv/start_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y101 FDRE (Prop_fdre_C_Q) 0.148 -0.869 r clkdv/start_cnt_reg[2]/Q + net (fo=4, routed) 0.157 -0.712 clkdv/p_0_in + SLICE_X54Y101 LUT2 (Prop_lut2_I0_O) 0.098 -0.614 f clkdv/buf100_i_1/O + net (fo=4, routed) 0.232 -0.382 clkdv/not_clock_enable + BUFGCTRL_X0Y16 BUFGCTRL r clkdv/buf12/CE0 (IS_INVERTED) + ------------------------------------------------------------------- ------------------- + + (clock clkout3 rise edge) 0.000 0.000 r + E3 0.000 0.000 r clk + net (fo=0) 0.000 0.000 clk + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r clk_IBUF_inst/O + net (fo=1, routed) 0.480 0.918 clkdv/clk_IBUF + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3) + -3.067 -2.149 r clkdv/mmcm/CLKOUT3 + net (fo=1, routed) 0.448 -1.702 clkdv/clkout3 + BUFGCTRL_X0Y16 r clkdv/buf12/I0 + clock pessimism 0.547 -1.155 + clock uncertainty 0.222 -0.933 + BUFGCTRL_X0Y16 BUFGCTRL (Hold_bufgctrl_I0_CE0) + 0.159 -0.774 clkdv/buf12 + ------------------------------------------------------------------- + required time 0.774 + arrival time -0.382 + ------------------------------------------------------------------- + slack 0.392 + + + + + diff --git a/Project.runs/impl_1/top_timing_summary_routed.rpx b/Project.runs/impl_1/top_timing_summary_routed.rpx new file mode 100644 index 0000000..597ce6f Binary files /dev/null and b/Project.runs/impl_1/top_timing_summary_routed.rpx differ diff --git a/Project.runs/impl_1/top_utilization_placed.pb b/Project.runs/impl_1/top_utilization_placed.pb new file mode 100644 index 0000000..95d2d25 Binary files /dev/null and b/Project.runs/impl_1/top_utilization_placed.pb differ diff --git a/Project.runs/impl_1/top_utilization_placed.rpt b/Project.runs/impl_1/top_utilization_placed.rpt new file mode 100644 index 0000000..86e3054 --- /dev/null +++ b/Project.runs/impl_1/top_utilization_placed.rpt @@ -0,0 +1,217 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:02:12 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb +| Design : top +| Device : xc7a100t +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs | 1347 | 0 | 63400 | 2.12 | +| LUT as Logic | 961 | 0 | 63400 | 1.51 | +| LUT as Memory | 386 | 0 | 19000 | 2.03 | +| LUT as Distributed RAM | 386 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 161 | 0 | 126800 | 0.12 | +| Register as Flip Flop | 161 | 0 | 126800 | 0.12 | +| Register as Latch | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 171 | 0 | 31700 | 0.53 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++----------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 161 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------------------------+----------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------------------------+----------+-------+-----------+-------+ +| Slice | 409 | 0 | 15850 | 2.58 | +| SLICEL | 249 | 0 | | | +| SLICEM | 160 | 0 | | | +| LUT as Logic | 961 | 0 | 63400 | 1.51 | +| using O5 output only | 0 | | | | +| using O6 output only | 798 | | | | +| using O5 and O6 | 163 | | | | +| LUT as Memory | 386 | 0 | 19000 | 2.03 | +| LUT as Distributed RAM | 386 | 0 | | | +| using O5 output only | 4 | | | | +| using O6 output only | 330 | | | | +| using O5 and O6 | 52 | | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 1414 | 0 | 63400 | 2.23 | +| fully used LUT-FF pairs | 71 | | | | +| LUT-FF pairs with unused LUT | 71 | | | | +| LUT-FF pairs with unused Flip Flop | 1272 | | | | +| Unique Control Sets | 25 | | | | +| Minimum number of registers lost to control set restriction | 39(Lost) | | | | ++-------------------------------------------------------------+----------+-------+-----------+-------+ + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 135 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 135 | 0.00 | +| RAMB18 | 0 | 0 | 270 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 240 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 34 | 34 | 210 | 16.19 | +| IOB Master Pads | 17 | | | | +| IOB Slave Pads | 17 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFGDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 3 | 0 | 32 | 9.37 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 1 | 0 | 6 | 16.66 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++------------+------+---------------------+ +| Ref Name | Used | Functional Category | ++------------+------+---------------------+ +| LUT6 | 560 | LUT | +| RAMD64E | 288 | Distributed Memory | +| LUT5 | 199 | LUT | +| MUXF7 | 171 | MuxFx | +| LUT4 | 167 | LUT | +| FDRE | 161 | Flop & Latch | +| LUT3 | 124 | LUT | +| RAMD32 | 84 | Distributed Memory | +| RAMS32 | 66 | Distributed Memory | +| LUT2 | 65 | LUT | +| CARRY4 | 36 | CarryLogic | +| OBUF | 30 | IO | +| LUT1 | 9 | LUT | +| IBUF | 4 | IO | +| BUFGCTRL | 2 | Clock | +| MMCME2_ADV | 1 | Clock | +| BUFG | 1 | Clock | ++------------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Project.runs/impl_1/usage_statistics_webtalk.html b/Project.runs/impl_1/usage_statistics_webtalk.html new file mode 100644 index 0000000..0e36106 --- /dev/null +++ b/Project.runs/impl_1/usage_statistics_webtalk.html @@ -0,0 +1,615 @@ +Device Usage Statistics Report +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
date_generatedWed Apr 22 08:04:26 2015product_versionVivado v2014.4 (64-bit)
build_version1071353os_platformWIN64
registration_id210990371_0_0_454tool_flowVivado
betaFALSEroute_designTRUE
target_familyartix7target_devicexc7a100t
target_packagecsg324target_speed-1
random_ideb5377b9525b5af7935fce46cb93c3f8project_id5f5d7ddd32cb4c0cb289603e426c9fed
project_iteration0

+ + + + + + + + +
user_environment
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
cpu_nameIntel(R) Core(TM) i5-3320M CPU @ 2.60GHzcpu_speed2594 MHz
total_processors1system_ram3.000 GB

+ + +
vivado_usage
+ + + + + + + + + + + + + + + +
project_data
srcsetcount=34constraintsetcount=1designmode=RTLprproject=false
reconfigpartitioncount=0reconfigmodulecount=0hdproject=falsepartitioncount=0
synthesisstrategy=Vivado Synthesis Defaultsimplstrategy=Vivado Implementation Defaultscurrentsynthesisrun=synth_1currentimplrun=impl_1
totalsynthesisruns=1totalimplruns=1
+
+ + + + +
unisim_transformation
+ + + + + + + + + + + + + + + + + + + + + + +
pre_unisim_transformation
bufg=1bufgctrl=4carry4=36fdre=161
gnd=10ibuf=4lut1=104lut2=65
lut3=124lut4=167lut5=199lut6=560
mmcme2_adv=1muxf7=27obuf=30ram128x1d=72
ram32m=12ram32x1d=16ram32x1s=32vcc=8
+
+ + + + + + + + + + + + + + + + + + + + + +
post_unisim_transformation
bufg=1bufgctrl=4carry4=36fdre=161
gnd=10ibuf=4lut1=104lut2=65
lut3=124lut4=167lut5=199lut6=560
mmcme2_adv=1muxf7=171obuf=30ramd32=104
ramd64e=288rams32=56vcc=8
+

+ + + +
placer
+ + + + + + + + + + + + + + + + + + + + + + +
usage
lut=1363ff=161bram36=0bram18=0
ctrls=25dsp=0iob=34bufg=0
global_clocks=3pll=0bufr=0nets=2120
movable_instances=1986pins=15924bogomips=0effort=2
threads=2placer_timing_driven=1timing_constraints_exist=1placer_runtime=10.416000
+

+ + + + +
report_power
+ + + + + + + + + + + + + +
command_line_options
-verbose=default::[not_specified]-hier=default::power-no_propagation=default::[not_specified]-format=default::text
-file=[specified]-name=default::[not_specified]-xpe=default::[not_specified]-return_string=default::[not_specified]
-vid=default::[not_specified]-append=default::[not_specified]-l=default::[not_specified]
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
customer=TBDcustomer_class=TBDflow_state=routedfamily=artix7
die=xc7a100tcsg324-1package=csg324speedgrade=-1version=2014.4
platform=nt64temp_grade=commercialprocess=typicalsimulation_file=None
netlist_net_matched=NApct_clock_constrained=1.000000pct_inputs_defined=25user_junc_temp=26.0 (C)
ambient_temp=25.0 (C)user_effective_thetaja=4.6airflow=250 (LFM)heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W)board_selection=medium (10"x10")board_layers=12to15 (12 to 15 Layers)user_thetajb=5.7 (C/W)
user_board_temp=25.0 (C)junction_temp=26.0 (C)input_toggle=12.500000output_toggle=12.500000
bi-dir_toggle=12.500000output_enable=1.000000bidir_output_enable=1.000000output_load=5.000000
ff_toggle=12.500000ram_enable=50.000000ram_write=50.000000dsp_output_toggle=12.500000
set/reset_probability=0.000000enable_probability=0.990000toggle_rate=Falsesignal_rate=False
static_prob=Falseread_saif=Falseon-chip_power=0.212289dynamic=0.114863
effective_thetaja=4.6thetasa=4.6 (C/W)thetajb=5.7 (C/W)off-chip_power=0.000000
clocks=0.001493logic=0.001739signals=0.001438mmcm=0.105905
i/o=0.004288devstatic=0.097426vccint_voltage=1.000000vccint_total_current=0.020461
vccint_dynamic_current=0.005181vccint_static_current=0.015280vccaux_voltage=1.800000vccaux_total_current=0.076908
vccaux_dynamic_current=0.058744vccaux_static_current=0.018164vcco33_voltage=3.300000vcco33_total_current=0.005195
vcco33_dynamic_current=0.001195vcco33_static_current=0.004000vcco25_voltage=2.500000vcco25_total_current=0.000000
vcco25_dynamic_current=0.000000vcco25_static_current=0.000000vcco18_voltage=1.800000vcco18_total_current=0.000000
vcco18_dynamic_current=0.000000vcco18_static_current=0.000000vcco15_voltage=1.500000vcco15_total_current=0.000000
vcco15_dynamic_current=0.000000vcco15_static_current=0.000000vcco135_voltage=1.350000vcco135_total_current=0.000000
vcco135_dynamic_current=0.000000vcco135_static_current=0.000000vcco12_voltage=1.200000vcco12_total_current=0.000000
vcco12_dynamic_current=0.000000vcco12_static_current=0.000000vccaux_io_voltage=1.800000vccaux_io_total_current=0.000000
vccaux_io_dynamic_current=0.000000vccaux_io_static_current=0.000000vccbram_voltage=1.000000vccbram_total_current=0.000250
vccbram_dynamic_current=0.000000vccbram_static_current=0.000250mgtavcc_voltage=1.000000mgtavcc_total_current=0.000000
mgtavcc_dynamic_current=0.000000mgtavcc_static_current=0.000000mgtavtt_voltage=1.200000mgtavtt_total_current=0.000000
mgtavtt_dynamic_current=0.000000mgtavtt_static_current=0.000000vccadc_voltage=1.800000vccadc_total_current=0.020000
vccadc_dynamic_current=0.000000vccadc_static_current=0.020000confidence_level_design_state=Highconfidence_level_clock_activity=High
confidence_level_io_activity=Mediumconfidence_level_internal_activity=Mediumconfidence_level_device_models=Highconfidence_level_overall=Medium
+

+ + + + + + + + + +
report_utilization
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
slice_logic
slice_luts_used=1347slice_luts_fixed=0slice_luts_available=63400slice_luts_util_percentage=2.12
lut_as_logic_used=961lut_as_logic_fixed=0lut_as_logic_available=63400lut_as_logic_util_percentage=1.51
lut_as_memory_used=386lut_as_memory_fixed=0lut_as_memory_available=19000lut_as_memory_util_percentage=2.03
lut_as_distributed_ram_used=386lut_as_distributed_ram_fixed=0lut_as_shift_register_used=0lut_as_shift_register_fixed=0
slice_registers_used=161slice_registers_fixed=0slice_registers_available=126800slice_registers_util_percentage=0.12
register_as_flip_flop_used=161register_as_flip_flop_fixed=0register_as_flip_flop_available=126800register_as_flip_flop_util_percentage=0.12
register_as_latch_used=0register_as_latch_fixed=0register_as_latch_available=126800register_as_latch_util_percentage=0.00
f7_muxes_used=171f7_muxes_fixed=0f7_muxes_available=31700f7_muxes_util_percentage=0.53
f8_muxes_used=0f8_muxes_fixed=0f8_muxes_available=15850f8_muxes_util_percentage=0.00
slice_used=409slice_fixed=0slice_available=15850slice_util_percentage=2.58
slicel_used=249slicel_fixed=0slicem_used=160slicem_fixed=0
lut_as_logic_used=961lut_as_logic_fixed=0lut_as_logic_available=63400lut_as_logic_util_percentage=1.51
using_o5_output_only_used=0using_o5_output_only_fixed=using_o6_output_only_used=798using_o6_output_only_fixed=
using_o5_and_o6_used=163using_o5_and_o6_fixed=lut_as_memory_used=386lut_as_memory_fixed=0
lut_as_memory_available=19000lut_as_memory_util_percentage=2.03lut_as_distributed_ram_used=386lut_as_distributed_ram_fixed=0
using_o5_output_only_used=4using_o5_output_only_fixed=using_o6_output_only_used=330using_o6_output_only_fixed=
using_o5_and_o6_used=52using_o5_and_o6_fixed=lut_as_shift_register_used=0lut_as_shift_register_fixed=0
lut_flip_flop_pairs_used=1414lut_flip_flop_pairs_fixed=0lut_flip_flop_pairs_available=63400lut_flip_flop_pairs_util_percentage=2.23
fully_used_lut_ff_pairs_used=71fully_used_lut_ff_pairs_fixed=lut_ff_pairs_with_unused_lut_used=71lut_ff_pairs_with_unused_lut_fixed=
lut_ff_pairs_with_unused_flip_flop_used=1272lut_ff_pairs_with_unused_flip_flop_fixed=unique_control_sets_used=25minimum_number_of_registers_lost_to_control_set_restriction_used=39(Lost)
+
+ + + + + + + + + + + + + + +
memory
block_ram_tile_used=0block_ram_tile_fixed=0block_ram_tile_available=135block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0ramb36_fifo*_fixed=0ramb36_fifo*_available=135ramb36_fifo*_util_percentage=0.00
ramb18_used=0ramb18_fixed=0ramb18_available=270ramb18_util_percentage=0.00
+
+ + + + + + +
dsp
dsps_used=0dsps_fixed=0dsps_available=240dsps_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
clocking
bufgctrl_used=3bufgctrl_fixed=0bufgctrl_available=32bufgctrl_util_percentage=9.37
bufio_used=0bufio_fixed=0bufio_available=24bufio_util_percentage=0.00
mmcme2_adv_used=1mmcme2_adv_fixed=0mmcme2_adv_available=6mmcme2_adv_util_percentage=16.66
plle2_adv_used=0plle2_adv_fixed=0plle2_adv_available=6plle2_adv_util_percentage=0.00
bufmrce_used=0bufmrce_fixed=0bufmrce_available=12bufmrce_util_percentage=0.00
bufhce_used=0bufhce_fixed=0bufhce_available=96bufhce_util_percentage=0.00
bufr_used=0bufr_fixed=0bufr_available=24bufr_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
specific_feature
bscane2_used=0bscane2_fixed=0bscane2_available=4bscane2_util_percentage=0.00
capturee2_used=0capturee2_fixed=0capturee2_available=1capturee2_util_percentage=0.00
dna_port_used=0dna_port_fixed=0dna_port_available=1dna_port_util_percentage=0.00
efuse_usr_used=0efuse_usr_fixed=0efuse_usr_available=1efuse_usr_util_percentage=0.00
frame_ecce2_used=0frame_ecce2_fixed=0frame_ecce2_available=1frame_ecce2_util_percentage=0.00
icape2_used=0icape2_fixed=0icape2_available=2icape2_util_percentage=0.00
pcie_2_1_used=0pcie_2_1_fixed=0pcie_2_1_available=1pcie_2_1_util_percentage=0.00
startupe2_used=0startupe2_fixed=0startupe2_available=1startupe2_util_percentage=0.00
xadc_used=0xadc_fixed=0xadc_available=1xadc_util_percentage=0.00
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
primitives
lut6_used=560lut6_functional_category=LUTramd64e_used=288ramd64e_functional_category=Distributed Memory
lut5_used=199lut5_functional_category=LUTmuxf7_used=171muxf7_functional_category=MuxFx
lut4_used=167lut4_functional_category=LUTfdre_used=161fdre_functional_category=Flop & Latch
lut3_used=124lut3_functional_category=LUTramd32_used=84ramd32_functional_category=Distributed Memory
rams32_used=66rams32_functional_category=Distributed Memorylut2_used=65lut2_functional_category=LUT
carry4_used=36carry4_functional_category=CarryLogicobuf_used=30obuf_functional_category=IO
lut1_used=9lut1_functional_category=LUTibuf_used=4ibuf_functional_category=IO
bufgctrl_used=2bufgctrl_functional_category=Clockmmcme2_adv_used=1mmcme2_adv_functional_category=Clock
bufg_used=1bufg_functional_category=Clock
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
io_standard
blvds_25=0lvcmos33=1sstl15_r=0lvttl=0
diff_sstl15=0hstl_ii=0diff_mobile_ddr=0lvcmos25=0
diff_sstl18_ii=0hstl_i=0mobile_ddr=0lvcmos12=0
sstl135_r=0lvcmos15=0lvcmos18=0pci33_3=0
hsul_12=0hstl_i_18=0diff_hsul_12=0hstl_ii_18=0
sstl18_i=0sstl18_ii=0sstl15=0sstl135=0
lvds_25=0diff_hstl_i=0rsds_25=0diff_hstl_ii=0
tmds_33=0diff_hstl_i_18=0mini_lvds_25=0diff_hstl_ii_18=0
ppds_25=0diff_sstl18_i=0diff_sstl15_r=0diff_sstl135=0
diff_sstl135_r=0
+

+ + + +
router
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
usage
lut=1499ff=161bram36=0bram18=0
ctrls=25dsp=0iob=34bufg=0
global_clocks=3pll=0bufr=0nets=2120
movable_instances=1986pins=15924bogomips=0high_fanout_nets=1
effort=2threads=2router_timing_driven=1timing_constraints_exist=1
congestion_level=0estimated_expansions=1471350actual_expansions=1507483router_runtime=50.072000
+

+ + + + +
synthesis
+ + + + + + + + + + + + + + + + + + + + + + +
command_line_options
-part=xc7a100tcsg324-1-name=default::[not_specified]-top=top-include_dirs=default::[not_specified]
-generic=default::[not_specified]-verilog_define=default::[not_specified]-constrset=default::[not_specified]-seu_protect=default::none
-flatten_hierarchy=default::rebuilt-gated_clock_conversion=default::off-directive=default::default-rtl=default::[not_specified]
-bufg=default::12-fanout_limit=default::10000-shreg_min_size=default::3-mode=default::default
-fsm_extraction=default::auto-keep_equivalent_registers=default::[not_specified]-resource_sharing=default::auto-control_set_opt_threshold=default::auto
+
+ + + + + + +
usage
elapsed=00:01:05smemory_peak=680.348MBmemory_gain=503.051MBhls_ip=0
+

+ + + +
xsim
+ + + + +
command_line_options
-sim_mode=default::behavioral-sim_type=default::
+

+ + diff --git a/Project.runs/impl_1/usage_statistics_webtalk.xml b/Project.runs/impl_1/usage_statistics_webtalk.xml new file mode 100644 index 0000000..83a5e18 --- /dev/null +++ b/Project.runs/impl_1/usage_statistics_webtalk.xml @@ -0,0 +1,557 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + + +
+
+ + + + +
+
+
+
+ + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + +
+
+
+
+ + + + + + + + + + + + + + +
+
+
+
+ + +
+
+
+ diff --git a/Project.runs/impl_1/vivado.jou b/Project.runs/impl_1/vivado.jou new file mode 100644 index 0000000..256be63 --- /dev/null +++ b/Project.runs/impl_1/vivado.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 08:01:21 2015 +# Process ID: 212 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/Project.runs/impl_1/vivado.pb b/Project.runs/impl_1/vivado.pb new file mode 100644 index 0000000..3d517f2 Binary files /dev/null and b/Project.runs/impl_1/vivado.pb differ diff --git a/Project.runs/impl_1/vivado_1016.backup.jou b/Project.runs/impl_1/vivado_1016.backup.jou new file mode 100644 index 0000000..c36a1c4 --- /dev/null +++ b/Project.runs/impl_1/vivado_1016.backup.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 07:08:03 2015 +# Process ID: 2636 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/Project.runs/impl_1/vivado_2244.backup.jou b/Project.runs/impl_1/vivado_2244.backup.jou new file mode 100644 index 0000000..1f54e59 --- /dev/null +++ b/Project.runs/impl_1/vivado_2244.backup.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 05:14:50 2015 +# Process ID: 4584 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/Project.runs/impl_1/vivado_4392.backup.jou b/Project.runs/impl_1/vivado_4392.backup.jou new file mode 100644 index 0000000..406a388 --- /dev/null +++ b/Project.runs/impl_1/vivado_4392.backup.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 02:01:47 2015 +# Process ID: 6268 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/Project.runs/impl_1/vivado_5308.backup.jou b/Project.runs/impl_1/vivado_5308.backup.jou new file mode 100644 index 0000000..a5d97b2 --- /dev/null +++ b/Project.runs/impl_1/vivado_5308.backup.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 07:28:16 2015 +# Process ID: 4760 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/Project.runs/impl_1/vivado_5436.backup.jou b/Project.runs/impl_1/vivado_5436.backup.jou new file mode 100644 index 0000000..9b39547 --- /dev/null +++ b/Project.runs/impl_1/vivado_5436.backup.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 01:26:13 2015 +# Process ID: 2588 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1/top.vdi +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/Project.runs/impl_1/write_bitstream.pb b/Project.runs/impl_1/write_bitstream.pb new file mode 100644 index 0000000..2d973c2 Binary files /dev/null and b/Project.runs/impl_1/write_bitstream.pb differ diff --git a/Project.runs/synth_1/.Vivado_Synthesis.queue.rst b/Project.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/synth_1/.vivado.begin.rst b/Project.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..2a3717e --- /dev/null +++ b/Project.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/Project.runs/synth_1/.vivado.end.rst b/Project.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/Project.runs/synth_1/ISEWrap.js b/Project.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..8a98177 --- /dev/null +++ b/Project.runs/synth_1/ISEWrap.js @@ -0,0 +1,196 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.close(); +} + +function ISEOpenFile( ISEFilename ) { + + var ISEFullPath = ISERunDir + "/" + ISEFilename; + return ISEFileSys.OpenTextFile( ISEFullPath, 8, true ); +} diff --git a/Project.runs/synth_1/ISEWrap.sh b/Project.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..2b3ebe0 --- /dev/null +++ b/Project.runs/synth_1/ISEWrap.sh @@ -0,0 +1,62 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL diff --git a/Project.runs/synth_1/bmem_init.txt b/Project.runs/synth_1/bmem_init.txt new file mode 100644 index 0000000..601a8d9 --- /dev/null +++ b/Project.runs/synth_1/bmem_init.txt @@ -0,0 +1,1280 @@ +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff \ No newline at end of file diff --git a/Project.runs/synth_1/dmem_init.txt b/Project.runs/synth_1/dmem_init.txt new file mode 100644 index 0000000..72cf8de --- /dev/null +++ b/Project.runs/synth_1/dmem_init.txt @@ -0,0 +1 @@ +0 // data memory not used in this program \ No newline at end of file diff --git a/Project.runs/synth_1/gen_run.xml b/Project.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..bdfda42 --- /dev/null +++ b/Project.runs/synth_1/gen_run.xml @@ -0,0 +1,342 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Project.runs/synth_1/htr.txt b/Project.runs/synth_1/htr.txt new file mode 100644 index 0000000..ec4104c --- /dev/null +++ b/Project.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log top.vds -m64 -mode batch -messageDb vivado.pb -source top.tcl diff --git a/Project.runs/synth_1/imem_init.txt b/Project.runs/synth_1/imem_init.txt new file mode 100644 index 0000000..f6fee7a --- /dev/null +++ b/Project.runs/synth_1/imem_init.txt @@ -0,0 +1,128 @@ +00000020 +201d203c +20100001 +20110028 +2012026c +20130029 +201403be +20150075 +20160072 +20170029 +200f0004 +8c086000 +1517fffe +20040014 +0c000075 +200404b0 +0c00001b +0c000030 +0c00004c +0c00005a +0c000025 +0c000068 +14400001 +0800000d +8c086000 +1517ffe8 +08000018 +23bdfffc +afa40000 +000f4020 +2084ffff +20894000 +ad280000 +1480fffc +8fa40000 +23bd0004 +03e00008 +22680000 +22890000 +200a0006 +ad004000 +ad204000 +21080028 +21290028 +214affff +1540fffa +ae404000 +03e00008 +02507020 +01d17020 +20080007 +00134820 +00145020 +11c90006 +11ca0005 +21290028 +214a0028 +2108ffff +1500fffa +08000043 +00108022 +0010402a +11000001 +08000042 +200f0001 +08000043 +200f0002 +000e402a +11000003 +200804b0 +010e402a +11000001 +00118822 +02509020 +02519020 +03e00008 +20040000 +0254402a +11000007 +08000052 +0284a020 +03e00008 +2008004e +1288fffc +2004ffd8 +08000050 +200803be +1288fff8 +20040028 +08000050 +20040000 +8c086000 +11150003 +11160006 +02649820 +03e00008 +20080029 +1268fffc +2004ffd8 +0800005e +20080399 +1268fff8 +20040028 +0800005e +20020000 +2008001d +20090000 +200a0027 +12490006 +124a0005 +2108ffff +21290028 +214a0028 +1500fffa +08000074 +20420001 +03e00008 +23bdfff8 +afbf0004 +afa40000 +00042400 +10800002 +2084ffff +1480fffe +8fa40000 +8fbf0004 +23bd0008 +03e00008 diff --git a/Project.runs/synth_1/regd_init.txt b/Project.runs/synth_1/regd_init.txt new file mode 100644 index 0000000..463fdf1 --- /dev/null +++ b/Project.runs/synth_1/regd_init.txt @@ -0,0 +1,32 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 \ No newline at end of file diff --git a/Project.runs/synth_1/rundef.js b/Project.runs/synth_1/rundef.js new file mode 100644 index 0000000..0741cd3 --- /dev/null +++ b/Project.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2014.4/bin;"; +} else { + PathVal = "C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2014.4/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log top.vds -m64 -mode batch -messageDb vivado.pb -source top.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/Project.runs/synth_1/runme.bat b/Project.runs/synth_1/runme.bat new file mode 100644 index 0000000..b93f7db --- /dev/null +++ b/Project.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/Project.runs/synth_1/runme.log b/Project.runs/synth_1/runme.log new file mode 100644 index 0000000..d648df1 --- /dev/null +++ b/Project.runs/synth_1/runme.log @@ -0,0 +1,671 @@ + +*** Running vivado + with args -log top.vds -m64 -mode batch -messageDb vivado.pb -source top.tcl + + +****** Vivado v2014.4 (64-bit) + **** SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 + **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 + ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. + +source top.tcl +# set_param gui.test TreeTableDev +# set_param xicom.use_bs_reader 1 +# debug::add_scope template.lib 1 +# set_msg_config -id {HDL 9-1061} -limit 100000 +# set_msg_config -id {HDL 9-1654} -limit 100000 +# create_project -in_memory -part xc7a100tcsg324-1 +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.0/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.1/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/0.9/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.0/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.1/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +# set_param project.compositeFile.enableAutoGeneration 0 +# set_param synth.vivado.isSynthRun true +# set_property webtalk.parent_dir C:/Users/jrpotter/Documents/Vivado/Project/Project.cache/wt [current_project] +# set_property parent.project_path C:/Users/jrpotter/Documents/Vivado/Project/Project.xpr [current_project] +# set_property default_lib xil_defaultlib [current_project] +# set_property target_language Verilog [current_project] +# read_verilog -library xil_defaultlib -sv { +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/initfile.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display640x480.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memory.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv +# } +# read_verilog -library xil_defaultlib { +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v +# } +# read_xdc C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc +# set_property used_in_implementation false [get_files C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +# catch { write_hwdef -file top.hwdef } +INFO: [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no block diagram instance in the design +# synth_design -top top -part xc7a100tcsg324-1 +Command: synth_design -top top -part xc7a100tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 232.199 ; gain = 74.242 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'top' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v:20] +INFO: [Synth 8-638] synthesizing module 'clockdivider_Nexys4' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv:10] + Parameter N bound to: 2 - type: integer +INFO: [Synth 8-638] synthesizing module 'MMCME2_BASE' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:16110] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter STARTUP_WAIT bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 40 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 80 - type: integer + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter REF_JITTER1 bound to: 0.010000 - type: float +INFO: [Synth 8-256] done synthesizing module 'MMCME2_BASE' (1#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:16110] +WARNING: [Synth 8-350] instance 'mmcm' of module 'MMCME2_BASE' requires 18 connections, but only 10 given [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv:14] +INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:606] +INFO: [Synth 8-256] done synthesizing module 'BUFG' (2#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:606] +INFO: [Synth 8-638] synthesizing module 'INV' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:12850] +INFO: [Synth 8-256] done synthesizing module 'INV' (3#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:12850] +INFO: [Synth 8-638] synthesizing module 'BUFGMUX' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:695] + Parameter CLK_SEL_TYPE bound to: ASYNC - type: string +INFO: [Synth 8-256] done synthesizing module 'BUFGMUX' (4#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:695] +INFO: [Synth 8-256] done synthesizing module 'clockdivider_Nexys4' (5#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv:10] +INFO: [Synth 8-638] synthesizing module 'imem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv:16] +INFO: [Synth 8-3876] $readmem data file 'imem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv:23] +INFO: [Synth 8-256] done synthesizing module 'imem' (6#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv:16] +INFO: [Synth 8-638] synthesizing module 'debouncer' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv:14] + Parameter N bound to: 20 - type: integer +INFO: [Synth 8-256] done synthesizing module 'debouncer' (7#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv:14] +INFO: [Synth 8-638] synthesizing module 'mips' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv:9] +INFO: [Synth 8-638] synthesizing module 'controller' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv:37] +INFO: [Synth 8-256] done synthesizing module 'controller' (8#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv:37] +INFO: [Synth 8-638] synthesizing module 'datapath' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:23] + Parameter Abits bound to: 5 - type: integer + Parameter Dbits bound to: 32 - type: integer + Parameter Nloc bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'register_file' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv:11] + Parameter Abits bound to: 5 - type: integer + Parameter Dbits bound to: 32 - type: integer + Parameter Nloc bound to: 32 - type: integer +INFO: [Synth 8-3876] $readmem data file 'regd_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv:24] +INFO: [Synth 8-256] done synthesizing module 'register_file' (9#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv:11] +WARNING: [Synth 8-689] width (32) of port connection 'WriteAddr' does not match port width (5) of module 'register_file' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:88] +INFO: [Synth 8-638] synthesizing module 'signExtension' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv:23] +INFO: [Synth 8-256] done synthesizing module 'signExtension' (10#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv:23] +INFO: [Synth 8-638] synthesizing module 'ALU' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'addsub' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'adder' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'fulladder' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v:23] +INFO: [Synth 8-256] done synthesizing module 'fulladder' (11#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v:23] +INFO: [Synth 8-256] done synthesizing module 'adder' (12#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v:23] +INFO: [Synth 8-256] done synthesizing module 'addsub' (13#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v:23] +INFO: [Synth 8-638] synthesizing module 'shifter' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shifter' (14#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v:23] +INFO: [Synth 8-638] synthesizing module 'logical' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-256] done synthesizing module 'logical' (15#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v:23] +INFO: [Synth 8-638] synthesizing module 'comparator' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-256] done synthesizing module 'comparator' (16#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v:23] +INFO: [Synth 8-256] done synthesizing module 'ALU' (17#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v:23] +INFO: [Synth 8-256] done synthesizing module 'datapath' (18#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:23] +INFO: [Synth 8-256] done synthesizing module 'mips' (19#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv:9] +INFO: [Synth 8-638] synthesizing module 'memIO' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:18] +INFO: [Synth 8-638] synthesizing module 'keyboard' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv:7] +INFO: [Synth 8-256] done synthesizing module 'keyboard' (20#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv:7] +INFO: [Synth 8-638] synthesizing module 'display8digit' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv:8] +INFO: [Synth 8-638] synthesizing module 'hexto7seg' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv:9] +INFO: [Synth 8-226] default block is never used [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv:15] +INFO: [Synth 8-256] done synthesizing module 'hexto7seg' (21#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv:9] +INFO: [Synth 8-256] done synthesizing module 'display8digit' (22#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv:8] +WARNING: [Synth 8-689] width (24) of port connection 'val' does not match port width (32) of module 'display8digit' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:91] +INFO: [Synth 8-638] synthesizing module 'smem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv:25] +INFO: [Synth 8-3876] $readmem data file 'smem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv:37] +INFO: [Synth 8-256] done synthesizing module 'smem' (23#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv:25] +WARNING: [Synth 8-689] width (32) of port connection 'writedata' does not match port width (8) of module 'smem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:102] +INFO: [Synth 8-638] synthesizing module 'dmem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv:15] +INFO: [Synth 8-3876] $readmem data file 'dmem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv:27] +INFO: [Synth 8-256] done synthesizing module 'dmem' (24#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv:15] +WARNING: [Synth 8-693] zero replication count - replication ignored [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:72] +INFO: [Synth 8-256] done synthesizing module 'memIO' (25#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:18] +INFO: [Synth 8-638] synthesizing module 'vgadisplaydriver' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv:15] +INFO: [Synth 8-638] synthesizing module 'vgatimer' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv:15] +INFO: [Synth 8-638] synthesizing module 'xycounter' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv:23] + Parameter width bound to: 800 - type: integer + Parameter height bound to: 525 - type: integer +INFO: [Synth 8-256] done synthesizing module 'xycounter' (26#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv:23] +INFO: [Synth 8-256] done synthesizing module 'vgatimer' (27#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv:15] +INFO: [Synth 8-638] synthesizing module 'bitmapmem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv:16] +INFO: [Synth 8-3876] $readmem data file 'bmem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv:23] +INFO: [Synth 8-256] done synthesizing module 'bitmapmem' (28#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv:16] +INFO: [Synth 8-256] done synthesizing module 'vgadisplaydriver' (29#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv:15] +INFO: [Synth 8-256] done synthesizing module 'top' (30#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v:20] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 265.379 ; gain = 107.422 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 265.379 ; gain = 107.422 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml +Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml +Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml +Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml... +Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml +Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml +Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +Finished Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 5 instances were transformed. + BUFGMUX => BUFGCTRL (inverted pins: CE0): 4 instances + MMCME2_BASE => MMCME2_ADV: 1 instances + +INFO: [Timing 38-2] Deriving generated clocks +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 582.031 ; gain = 0.023 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +ROM "mem" won't be mapped to RAM because it is too sparse. +ROM "count" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +ROM "x" won't be mapped to RAM because it is too sparse. +ROM "y0" won't be mapped to RAM because it is too sparse. +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 3 + 2 Input 11 Bit Adders := 2 + 2 Input 10 Bit Adders := 2 + 2 Input 4 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 2 + 2 Input 1 Bit XORs := 67 ++---Registers : + 32 Bit Registers := 1 + 24 Bit Registers := 1 + 10 Bit Registers := 3 + 4 Bit Registers := 1 + 3 Bit Registers := 1 + 2 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 129 Input 32 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 17 + 5 Input 32 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 2 + 5 Input 10 Bit Muxes := 1 + 9 Input 10 Bit Muxes := 1 + 16 Input 8 Bit Muxes := 1 + 8 Input 8 Bit Muxes := 1 + 12 Input 5 Bit Muxes := 1 + 6 Input 5 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 3 + 2 Input 4 Bit Muxes := 3 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 6 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module top +Detailed RTL Component Info : +Module clockdivider_Nexys4 +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 3 Bit Registers := 1 +Module imem +Detailed RTL Component Info : ++---Muxes : + 129 Input 32 Bit Muxes := 1 +Module debouncer +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 1 +Module controller +Detailed RTL Component Info : ++---Muxes : + 5 Input 10 Bit Muxes := 1 + 9 Input 10 Bit Muxes := 1 + 12 Input 5 Bit Muxes := 1 + 6 Input 5 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 +Module register_file +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 2 +Module signExtension +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 1 +Module fulladder +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module adder +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 +Module addsub +Detailed RTL Component Info : ++---XORs : + 2 Input 32 Bit XORs := 1 +Module shifter +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 2 +Module logical +Detailed RTL Component Info : ++---XORs : + 2 Input 32 Bit XORs := 1 ++---Muxes : + 5 Input 32 Bit Muxes := 1 +Module comparator +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ALU +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 3 +Module datapath +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 2 ++---Registers : + 32 Bit Registers := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 7 + 2 Input 5 Bit Muxes := 3 +Module mips +Detailed RTL Component Info : +Module keyboard +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 24 Bit Registers := 1 + 10 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 24 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module hexto7seg +Detailed RTL Component Info : ++---Muxes : + 16 Input 8 Bit Muxes := 1 +Module display8digit +Detailed RTL Component Info : ++---Muxes : + 8 Input 8 Bit Muxes := 1 +Module smem +Detailed RTL Component Info : +Module dmem +Detailed RTL Component Info : +Module memIO +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 2 Input 24 Bit Muxes := 1 +Module xycounter +Detailed RTL Component Info : ++---Adders : + 2 Input 11 Bit Adders := 2 + 2 Input 10 Bit Adders := 2 ++---Registers : + 10 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module vgatimer +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 2 Bit Registers := 1 +Module bitmapmem +Detailed RTL Component Info : +Module vgadisplaydriver +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Start Cross Boundary Optimization +--------------------------------------------------------------------------------- +ROM "timer/xy/x" won't be mapped to RAM because it is too sparse. +ROM "timer/xy/y0" won't be mapped to RAM because it is too sparse. +--------------------------------------------------------------------------------- +Finished Cross Boundary Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Finished Parallel Reinference : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: ++------------+-------------------+--------------------+----------------------+----------------------------------------------+-------------------+ +|Module Name | RTL Object | Inference Criteria | Size (depth X width) | Primitives | Hierarchical Name | ++------------+-------------------+--------------------+----------------------+----------------------------------------------+-------------------+ +|top | mips/dp/rf/rf_reg | Implied | 32 X 32 | RAM32M x 12 | top/ram__6 | +|top | io/smem/mem_reg | Implied | 2 K X 8 | RAM16X1D x 8 RAM32X1D x 8 RAM128X1D x 72 | top/ram__8 | +|top | io/dmem/mem_reg | Implied | 32 X 32 | RAM32X1S x 32 | top/ram__10 | ++------------+-------------------+--------------------+----------------------+----------------------------------------------+-------------------+ + +Note: The table shows RAMs generated at current stage. Some RAM generation could be reversed due to later optimizations. Multiple instantiated RAMs are reported only once. "Hierarchical Name" reflects the hierarchical modules names of the RAM and only part of it is displayed. +--------------------------------------------------------------------------------- +Finished RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[18] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[19] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[20] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[21] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[22] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[23] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[24] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[25] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[26] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[27] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[28] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[29] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[30] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[31] ) is unused and will be removed from module top. +--------------------------------------------------------------------------------- +Start Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Finished Parallel Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:55 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:55 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:55 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |BUFG | 1| +|2 |BUFGMUX | 4| +|3 |CARRY4 | 36| +|4 |LUT1 | 104| +|5 |LUT2 | 65| +|6 |LUT3 | 124| +|7 |LUT4 | 167| +|8 |LUT5 | 199| +|9 |LUT6 | 560| +|10 |MMCME2_BASE | 1| +|11 |MUXF7 | 27| +|12 |RAM128X1D | 72| +|13 |RAM16X1D | 8| +|14 |RAM32M | 12| +|15 |RAM32X1D | 8| +|16 |RAM32X1S | 32| +|17 |FDRE | 161| +|18 |IBUF | 4| +|19 |OBUF | 30| ++------+------------+------+ + +Report Instance Areas: ++------+----------------+--------------------+------+ +| |Instance |Module |Cells | ++------+----------------+--------------------+------+ +|1 |top | | 1615| +|2 | clkdv |clockdivider_Nexys4 | 13| +|3 | displaydriver |vgadisplaydriver | 99| +|4 | timer |vgatimer | 80| +|5 | xy |xycounter | 76| +|6 | io |memIO | 333| +|7 | disp |display8digit | 50| +|8 | dmem |dmem | 36| +|9 | kmem |keyboard | 143| +|10 | smem |smem | 104| +|11 | mips |mips | 1084| +|12 | dp |datapath | 1084| +|13 | rf |register_file | 1011| +|14 | rbouncer |debouncer | 52| ++------+----------------+--------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 14 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:55 . Memory (MB): peak = 680.348 ; gain = 186.336 +Synthesis Optimization Complete : Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 680.348 ; gain = 522.391 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 177 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 137 instances were transformed. + BUFGMUX => BUFGCTRL (inverted pins: CE0): 4 instances + MMCME2_BASE => MMCME2_ADV: 1 instances + RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 72 instances + RAM16X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances + RAM32X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32X1S => RAM32X1S (RAMS32): 32 instances + +INFO: [Common 17-83] Releasing license: Synthesis +81 Infos, 19 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 680.348 ; gain = 503.051 +# write_checkpoint -noxdef top.dcp +# catch { report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb } +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.172 . Memory (MB): peak = 680.348 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Wed Apr 22 08:01:16 2015... diff --git a/Project.runs/synth_1/runme.sh b/Project.runs/synth_1/runme.sh new file mode 100644 index 0000000..9d842d8 --- /dev/null +++ b/Project.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2014.4/bin +else + PATH=C:/Xilinx/Vivado/2014.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2014.4/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2014.4/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD=`dirname "$0"` +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log top.vds -m64 -mode batch -messageDb vivado.pb -source top.tcl diff --git a/Project.runs/synth_1/smem_init.txt b/Project.runs/synth_1/smem_init.txt new file mode 100644 index 0000000..902e18d --- /dev/null +++ b/Project.runs/synth_1/smem_init.txt @@ -0,0 +1,1200 @@ +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 \ No newline at end of file diff --git a/Project.runs/synth_1/top.dcp b/Project.runs/synth_1/top.dcp new file mode 100644 index 0000000..f7e9944 Binary files /dev/null and b/Project.runs/synth_1/top.dcp differ diff --git a/Project.runs/synth_1/top.tcl b/Project.runs/synth_1/top.tcl new file mode 100644 index 0000000..ebcfc4f --- /dev/null +++ b/Project.runs/synth_1/top.tcl @@ -0,0 +1,57 @@ +# +# Synthesis run script generated by Vivado +# + +set_param gui.test TreeTableDev +set_param xicom.use_bs_reader 1 +debug::add_scope template.lib 1 +set_msg_config -id {HDL 9-1061} -limit 100000 +set_msg_config -id {HDL 9-1654} -limit 100000 + +create_project -in_memory -part xc7a100tcsg324-1 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/jrpotter/Documents/Vivado/Project/Project.cache/wt [current_project] +set_property parent.project_path C:/Users/jrpotter/Documents/Vivado/Project/Project.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +read_verilog -library xil_defaultlib -sv { + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/initfile.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display640x480.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memory.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv +} +read_verilog -library xil_defaultlib { + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v + C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v +} +read_xdc C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc +set_property used_in_implementation false [get_files C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] + +catch { write_hwdef -file top.hwdef } +synth_design -top top -part xc7a100tcsg324-1 +write_checkpoint -noxdef top.dcp +catch { report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb } diff --git a/Project.runs/synth_1/top.vds b/Project.runs/synth_1/top.vds new file mode 100644 index 0000000..73612cc --- /dev/null +++ b/Project.runs/synth_1/top.vds @@ -0,0 +1,670 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 08:00:07 2015 +# Process ID: 5712 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/synth_1/top.vds +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source top.tcl +# set_param gui.test TreeTableDev +# set_param xicom.use_bs_reader 1 +# debug::add_scope template.lib 1 +# set_msg_config -id {HDL 9-1061} -limit 100000 +# set_msg_config -id {HDL 9-1654} -limit 100000 +# create_project -in_memory -part xc7a100tcsg324-1 +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/0.9/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.0/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/kintex7/kc705/1.1/board_part.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:0.9 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/0.9/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.0 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.0/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.1 available at C:/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/zc706/1.1/board_part.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +# set_param project.compositeFile.enableAutoGeneration 0 +# set_param synth.vivado.isSynthRun true +# set_property webtalk.parent_dir C:/Users/jrpotter/Documents/Vivado/Project/Project.cache/wt [current_project] +# set_property parent.project_path C:/Users/jrpotter/Documents/Vivado/Project/Project.xpr [current_project] +# set_property default_lib xil_defaultlib [current_project] +# set_property target_language Verilog [current_project] +# read_verilog -library xil_defaultlib -sv { +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/initfile.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display640x480.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memory.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv +# } +# read_verilog -library xil_defaultlib { +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v +# C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v +# } +# read_xdc C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc +# set_property used_in_implementation false [get_files C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +# catch { write_hwdef -file top.hwdef } +INFO: [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no block diagram instance in the design +# synth_design -top top -part xc7a100tcsg324-1 +Command: synth_design -top top -part xc7a100tcsg324-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 232.199 ; gain = 74.242 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'top' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v:20] +INFO: [Synth 8-638] synthesizing module 'clockdivider_Nexys4' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv:10] + Parameter N bound to: 2 - type: integer +INFO: [Synth 8-638] synthesizing module 'MMCME2_BASE' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:16110] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter STARTUP_WAIT bound to: FALSE - type: string + Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 40 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 80 - type: integer + Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: float + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float + Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float + Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float + Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float + Parameter REF_JITTER1 bound to: 0.010000 - type: float +INFO: [Synth 8-256] done synthesizing module 'MMCME2_BASE' (1#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:16110] +WARNING: [Synth 8-350] instance 'mmcm' of module 'MMCME2_BASE' requires 18 connections, but only 10 given [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv:14] +INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:606] +INFO: [Synth 8-256] done synthesizing module 'BUFG' (2#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:606] +INFO: [Synth 8-638] synthesizing module 'INV' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:12850] +INFO: [Synth 8-256] done synthesizing module 'INV' (3#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:12850] +INFO: [Synth 8-638] synthesizing module 'BUFGMUX' [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:695] + Parameter CLK_SEL_TYPE bound to: ASYNC - type: string +INFO: [Synth 8-256] done synthesizing module 'BUFGMUX' (4#1) [C:/Xilinx/Vivado/2014.4/scripts/rt/data/unisim_comp.v:695] +INFO: [Synth 8-256] done synthesizing module 'clockdivider_Nexys4' (5#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv:10] +INFO: [Synth 8-638] synthesizing module 'imem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv:16] +INFO: [Synth 8-3876] $readmem data file 'imem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv:23] +INFO: [Synth 8-256] done synthesizing module 'imem' (6#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv:16] +INFO: [Synth 8-638] synthesizing module 'debouncer' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv:14] + Parameter N bound to: 20 - type: integer +INFO: [Synth 8-256] done synthesizing module 'debouncer' (7#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv:14] +INFO: [Synth 8-638] synthesizing module 'mips' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv:9] +INFO: [Synth 8-638] synthesizing module 'controller' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv:37] +INFO: [Synth 8-256] done synthesizing module 'controller' (8#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv:37] +INFO: [Synth 8-638] synthesizing module 'datapath' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:23] + Parameter Abits bound to: 5 - type: integer + Parameter Dbits bound to: 32 - type: integer + Parameter Nloc bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'register_file' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv:11] + Parameter Abits bound to: 5 - type: integer + Parameter Dbits bound to: 32 - type: integer + Parameter Nloc bound to: 32 - type: integer +INFO: [Synth 8-3876] $readmem data file 'regd_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv:24] +INFO: [Synth 8-256] done synthesizing module 'register_file' (9#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv:11] +WARNING: [Synth 8-689] width (32) of port connection 'WriteAddr' does not match port width (5) of module 'register_file' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:88] +INFO: [Synth 8-638] synthesizing module 'signExtension' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv:23] +INFO: [Synth 8-256] done synthesizing module 'signExtension' (10#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv:23] +INFO: [Synth 8-638] synthesizing module 'ALU' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'addsub' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'adder' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-638] synthesizing module 'fulladder' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v:23] +INFO: [Synth 8-256] done synthesizing module 'fulladder' (11#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v:23] +INFO: [Synth 8-256] done synthesizing module 'adder' (12#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v:23] +INFO: [Synth 8-256] done synthesizing module 'addsub' (13#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v:23] +INFO: [Synth 8-638] synthesizing module 'shifter' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-256] done synthesizing module 'shifter' (14#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v:23] +INFO: [Synth 8-638] synthesizing module 'logical' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-256] done synthesizing module 'logical' (15#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v:23] +INFO: [Synth 8-638] synthesizing module 'comparator' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v:23] + Parameter N bound to: 32 - type: integer +INFO: [Synth 8-256] done synthesizing module 'comparator' (16#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v:23] +INFO: [Synth 8-256] done synthesizing module 'ALU' (17#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v:23] +INFO: [Synth 8-256] done synthesizing module 'datapath' (18#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:23] +INFO: [Synth 8-256] done synthesizing module 'mips' (19#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv:9] +INFO: [Synth 8-638] synthesizing module 'memIO' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:18] +INFO: [Synth 8-638] synthesizing module 'keyboard' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv:7] +INFO: [Synth 8-256] done synthesizing module 'keyboard' (20#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/keyboard.sv:7] +INFO: [Synth 8-638] synthesizing module 'display8digit' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv:8] +INFO: [Synth 8-638] synthesizing module 'hexto7seg' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv:9] +INFO: [Synth 8-226] default block is never used [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv:15] +INFO: [Synth 8-256] done synthesizing module 'hexto7seg' (21#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/hexto7seg.sv:9] +INFO: [Synth 8-256] done synthesizing module 'display8digit' (22#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/display8digit.sv:8] +WARNING: [Synth 8-689] width (24) of port connection 'val' does not match port width (32) of module 'display8digit' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:91] +INFO: [Synth 8-638] synthesizing module 'smem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv:25] +INFO: [Synth 8-3876] $readmem data file 'smem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv:37] +INFO: [Synth 8-256] done synthesizing module 'smem' (23#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv:25] +WARNING: [Synth 8-689] width (32) of port connection 'writedata' does not match port width (8) of module 'smem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:102] +INFO: [Synth 8-638] synthesizing module 'dmem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv:15] +INFO: [Synth 8-3876] $readmem data file 'dmem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv:27] +INFO: [Synth 8-256] done synthesizing module 'dmem' (24#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv:15] +WARNING: [Synth 8-693] zero replication count - replication ignored [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:72] +INFO: [Synth 8-256] done synthesizing module 'memIO' (25#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:18] +INFO: [Synth 8-638] synthesizing module 'vgadisplaydriver' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv:15] +INFO: [Synth 8-638] synthesizing module 'vgatimer' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv:15] +INFO: [Synth 8-638] synthesizing module 'xycounter' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv:23] + Parameter width bound to: 800 - type: integer + Parameter height bound to: 525 - type: integer +INFO: [Synth 8-256] done synthesizing module 'xycounter' (26#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv:23] +INFO: [Synth 8-256] done synthesizing module 'vgatimer' (27#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv:15] +INFO: [Synth 8-638] synthesizing module 'bitmapmem' [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv:16] +INFO: [Synth 8-3876] $readmem data file 'bmem_init.txt' is read successfully [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv:23] +INFO: [Synth 8-256] done synthesizing module 'bitmapmem' (28#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv:16] +INFO: [Synth 8-256] done synthesizing module 'vgadisplaydriver' (29#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv:15] +INFO: [Synth 8-256] done synthesizing module 'top' (30#1) [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v:20] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 265.379 ; gain = 107.422 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 265.379 ; gain = 107.422 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml +Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml +Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml +Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml... +Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml +Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml +Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +Finished Parsing XDC File [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/constrs_1/imports/src/master.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 5 instances were transformed. + BUFGMUX => BUFGCTRL (inverted pins: CE0): 4 instances + MMCME2_BASE => MMCME2_ADV: 1 instances + +INFO: [Timing 38-2] Deriving generated clocks +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 582.031 ; gain = 0.023 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +ROM "mem" won't be mapped to RAM because it is too sparse. +ROM "count" won't be mapped to Block RAM because address size (2) smaller than threshold (5) +ROM "x" won't be mapped to RAM because it is too sparse. +ROM "y0" won't be mapped to RAM because it is too sparse. +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 3 + 2 Input 11 Bit Adders := 2 + 2 Input 10 Bit Adders := 2 + 2 Input 4 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 ++---XORs : + 2 Input 32 Bit XORs := 2 + 2 Input 1 Bit XORs := 67 ++---Registers : + 32 Bit Registers := 1 + 24 Bit Registers := 1 + 10 Bit Registers := 3 + 4 Bit Registers := 1 + 3 Bit Registers := 1 + 2 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 129 Input 32 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 17 + 5 Input 32 Bit Muxes := 1 + 2 Input 24 Bit Muxes := 2 + 5 Input 10 Bit Muxes := 1 + 9 Input 10 Bit Muxes := 1 + 16 Input 8 Bit Muxes := 1 + 8 Input 8 Bit Muxes := 1 + 12 Input 5 Bit Muxes := 1 + 6 Input 5 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 3 + 2 Input 4 Bit Muxes := 3 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 6 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module top +Detailed RTL Component Info : +Module clockdivider_Nexys4 +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 3 Bit Registers := 1 +Module imem +Detailed RTL Component Info : ++---Muxes : + 129 Input 32 Bit Muxes := 1 +Module debouncer +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 1 +Module controller +Detailed RTL Component Info : ++---Muxes : + 5 Input 10 Bit Muxes := 1 + 9 Input 10 Bit Muxes := 1 + 12 Input 5 Bit Muxes := 1 + 6 Input 5 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 2 + 2 Input 1 Bit Muxes := 1 +Module register_file +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 2 +Module signExtension +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 1 +Module fulladder +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module adder +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 +Module addsub +Detailed RTL Component Info : ++---XORs : + 2 Input 32 Bit XORs := 1 +Module shifter +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 2 +Module logical +Detailed RTL Component Info : ++---XORs : + 2 Input 32 Bit XORs := 1 ++---Muxes : + 5 Input 32 Bit Muxes := 1 +Module comparator +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ALU +Detailed RTL Component Info : ++---Muxes : + 2 Input 32 Bit Muxes := 3 +Module datapath +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 2 ++---Registers : + 32 Bit Registers := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 7 + 2 Input 5 Bit Muxes := 3 +Module mips +Detailed RTL Component Info : +Module keyboard +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 24 Bit Registers := 1 + 10 Bit Registers := 1 + 4 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 24 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module hexto7seg +Detailed RTL Component Info : ++---Muxes : + 16 Input 8 Bit Muxes := 1 +Module display8digit +Detailed RTL Component Info : ++---Muxes : + 8 Input 8 Bit Muxes := 1 +Module smem +Detailed RTL Component Info : +Module dmem +Detailed RTL Component Info : +Module memIO +Detailed RTL Component Info : ++---Adders : + 2 Input 32 Bit Adders := 1 ++---Muxes : + 2 Input 32 Bit Muxes := 2 + 2 Input 24 Bit Muxes := 1 +Module xycounter +Detailed RTL Component Info : ++---Adders : + 2 Input 11 Bit Adders := 2 + 2 Input 10 Bit Adders := 2 ++---Registers : + 10 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module vgatimer +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 2 Bit Registers := 1 +Module bitmapmem +Detailed RTL Component Info : +Module vgadisplaydriver +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 3 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Start Cross Boundary Optimization +--------------------------------------------------------------------------------- +ROM "timer/xy/x" won't be mapped to RAM because it is too sparse. +ROM "timer/xy/y0" won't be mapped to RAM because it is too sparse. +--------------------------------------------------------------------------------- +Finished Cross Boundary Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Finished Parallel Reinference : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 582.031 ; gain = 424.074 + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: ++------------+-------------------+--------------------+----------------------+----------------------------------------------+-------------------+ +|Module Name | RTL Object | Inference Criteria | Size (depth X width) | Primitives | Hierarchical Name | ++------------+-------------------+--------------------+----------------------+----------------------------------------------+-------------------+ +|top | mips/dp/rf/rf_reg | Implied | 32 X 32 | RAM32M x 12 | top/ram__6 | +|top | io/smem/mem_reg | Implied | 2 K X 8 | RAM16X1D x 8 RAM32X1D x 8 RAM128X1D x 72 | top/ram__8 | +|top | io/dmem/mem_reg | Implied | 32 X 32 | RAM32X1S x 32 | top/ram__10 | ++------------+-------------------+--------------------+----------------------+----------------------------------------------+-------------------+ + +Note: The table shows RAMs generated at current stage. Some RAM generation could be reversed due to later optimizations. Multiple instantiated RAMs are reported only once. "Hierarchical Name" reflects the hierarchical modules names of the RAM and only part of it is displayed. +--------------------------------------------------------------------------------- +Finished RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[18] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[19] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[20] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[21] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[22] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[23] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[24] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[25] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[26] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[27] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[28] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[29] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[30] ) is unused and will be removed from module top. +WARNING: [Synth 8-3332] Sequential element (\io/disp/counter_reg[31] ) is unused and will be removed from module top. +--------------------------------------------------------------------------------- +Start Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Finished Parallel Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:36 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 582.031 ; gain = 424.074 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:55 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:55 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:55 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |BUFG | 1| +|2 |BUFGMUX | 4| +|3 |CARRY4 | 36| +|4 |LUT1 | 104| +|5 |LUT2 | 65| +|6 |LUT3 | 124| +|7 |LUT4 | 167| +|8 |LUT5 | 199| +|9 |LUT6 | 560| +|10 |MMCME2_BASE | 1| +|11 |MUXF7 | 27| +|12 |RAM128X1D | 72| +|13 |RAM16X1D | 8| +|14 |RAM32M | 12| +|15 |RAM32X1D | 8| +|16 |RAM32X1S | 32| +|17 |FDRE | 161| +|18 |IBUF | 4| +|19 |OBUF | 30| ++------+------------+------+ + +Report Instance Areas: ++------+----------------+--------------------+------+ +| |Instance |Module |Cells | ++------+----------------+--------------------+------+ +|1 |top | | 1615| +|2 | clkdv |clockdivider_Nexys4 | 13| +|3 | displaydriver |vgadisplaydriver | 99| +|4 | timer |vgatimer | 80| +|5 | xy |xycounter | 76| +|6 | io |memIO | 333| +|7 | disp |display8digit | 50| +|8 | dmem |dmem | 36| +|9 | kmem |keyboard | 143| +|10 | smem |smem | 104| +|11 | mips |mips | 1084| +|12 | dp |datapath | 1084| +|13 | rf |register_file | 1011| +|14 | rbouncer |debouncer | 52| ++------+----------------+--------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 680.348 ; gain = 522.391 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 14 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:55 . Memory (MB): peak = 680.348 ; gain = 186.336 +Synthesis Optimization Complete : Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 680.348 ; gain = 522.391 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 177 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. +INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 137 instances were transformed. + BUFGMUX => BUFGCTRL (inverted pins: CE0): 4 instances + MMCME2_BASE => MMCME2_ADV: 1 instances + RAM128X1D => RAM128X1D (RAMD64E, RAMD64E, MUXF7, MUXF7, RAMD64E, RAMD64E): 72 instances + RAM16X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 12 instances + RAM32X1D => RAM32X1D (RAMD32, RAMD32): 8 instances + RAM32X1S => RAM32X1S (RAMS32): 32 instances + +INFO: [Common 17-83] Releasing license: Synthesis +81 Infos, 19 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:07 . Memory (MB): peak = 680.348 ; gain = 503.051 +# write_checkpoint -noxdef top.dcp +# catch { report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb } +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.172 . Memory (MB): peak = 680.348 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Wed Apr 22 08:01:16 2015... diff --git a/Project.runs/synth_1/top_utilization_synth.pb b/Project.runs/synth_1/top_utilization_synth.pb new file mode 100644 index 0000000..94a0793 Binary files /dev/null and b/Project.runs/synth_1/top_utilization_synth.pb differ diff --git a/Project.runs/synth_1/top_utilization_synth.rpt b/Project.runs/synth_1/top_utilization_synth.rpt new file mode 100644 index 0000000..988fa68 --- /dev/null +++ b/Project.runs/synth_1/top_utilization_synth.rpt @@ -0,0 +1,187 @@ +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014 +| Date : Wed Apr 22 08:01:16 2015 +| Host : jrpotter running 64-bit major release (build 9200) +| Command : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb +| Design : top +| Device : xc7a100t +| Design State : Synthesized +------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1468 | 0 | 63400 | 2.31 | +| LUT as Logic | 1068 | 0 | 63400 | 1.68 | +| LUT as Memory | 400 | 0 | 19000 | 2.10 | +| LUT as Distributed RAM | 400 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 161 | 0 | 126800 | 0.12 | +| Register as Flip Flop | 161 | 0 | 126800 | 0.12 | +| Register as Latch | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 171 | 0 | 31700 | 0.53 | +| F8 Muxes | 0 | 0 | 15850 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 161 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 135 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 135 | 0.00 | +| RAMB18 | 0 | 0 | 270 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 240 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 34 | 0 | 210 | 16.19 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 0 | 0 | 6 | 0.00 | +| PHASER_REF | 0 | 0 | 6 | 0.00 | +| OUT_FIFO | 0 | 0 | 24 | 0.00 | +| IN_FIFO | 0 | 0 | 24 | 0.00 | +| IDELAYCTRL | 0 | 0 | 6 | 0.00 | +| IBUFGDS | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | +| ILOGIC | 0 | 0 | 210 | 0.00 | +| OLOGIC | 0 | 0 | 210 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 32 | 15.62 | +| BUFIO | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 1 | 0 | 6 | 16.66 | +| PLLE2_ADV | 0 | 0 | 6 | 0.00 | +| BUFMRCE | 0 | 0 | 12 | 0.00 | +| BUFHCE | 0 | 0 | 96 | 0.00 | +| BUFR | 0 | 0 | 24 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++------------+------+---------------------+ +| Ref Name | Used | Functional Category | ++------------+------+---------------------+ +| LUT6 | 560 | LUT | +| RAMD64E | 288 | Distributed Memory | +| LUT5 | 199 | LUT | +| MUXF7 | 171 | MuxFx | +| LUT4 | 167 | LUT | +| FDRE | 161 | Flop & Latch | +| LUT3 | 124 | LUT | +| RAMD32 | 104 | Distributed Memory | +| LUT1 | 104 | LUT | +| LUT2 | 65 | LUT | +| RAMS32 | 56 | Distributed Memory | +| CARRY4 | 36 | CarryLogic | +| OBUF | 30 | IO | +| IBUF | 4 | IO | +| BUFGCTRL | 4 | Clock | +| MMCME2_ADV | 1 | Clock | +| BUFG | 1 | Clock | ++------------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/Project.runs/synth_1/vivado.jou b/Project.runs/synth_1/vivado.jou new file mode 100644 index 0000000..09e7689 --- /dev/null +++ b/Project.runs/synth_1/vivado.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Vivado v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Wed Apr 22 08:00:07 2015 +# Process ID: 5712 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/synth_1/top.vds +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source top.tcl diff --git a/Project.runs/synth_1/vivado.pb b/Project.runs/synth_1/vivado.pb new file mode 100644 index 0000000..078543b Binary files /dev/null and b/Project.runs/synth_1/vivado.pb differ diff --git a/Project.sim/sim_1/behav/Lab10_test_sqr.sv b/Project.sim/sim_1/behav/Lab10_test_sqr.sv new file mode 100644 index 0000000..94fa3ac --- /dev/null +++ b/Project.sim/sim_1/behav/Lab10_test_sqr.sv @@ -0,0 +1,246 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 3/26/2015 +// +// This is a self-checking tester for your full MIPS processor +// (Lab 10 and Project). Use the 2nd test program provided under Lab 10, +// i.e., initialize instruction memory with test2.txt, and data memory +// with test2_data.txt. +// +// Use this tester carefully! The names of your top-level input/output +// and internal signals may be different, so modify all of signal names on the +// right-hand-side of the "wire" assigments appearing above the uut +// instantiation. Observe that the uut itself only has clock and reset inputs +// now, and no debug outputs. Instead, the internal signals are "pulled out" +// using the member selection, or dot, operator ("."). +// +// If you decide not to use some of these internal signals for debugging, you +// may comment the relevant lines out. Be sure to comment out the +// corresponding "ERROR_*" lines below as well. +// +////////////////////////////////////////////////////////////////////////////////// + + +module mips_test_sqr; + + // Inputs + reg clk; + reg reset; + + // Signals inside top-level module uut + wire [31:0] pc =uut.pc; // PC + wire [31:0] instr =uut.instr; // instr coming out of instr mem + wire [31:0] mem_addr =uut.mem_addr; // addr sent to data mem + wire mem_wr =uut.mem_wr; // write enable for data mem + wire [31:0] mem_readdata =uut.mem_readdata; // data read from data mem + wire [31:0] mem_writedata =uut.mem_writedata; // write data for data mem + + // Signals inside module uut.mips + wire werf =uut.mips.werf; // WERF = write enable for register file + wire [4:0] alufn =uut.mips.alufn; // ALU function + wire Z =uut.mips.Z; // Zero flag + + // Signals inside module uut.mips.dp (datapath) + wire [31:0] ReadData1 =uut.mips.dp.ReadData1; // Reg[rs] + wire [31:0] ReadData2 =uut.mips.dp.ReadData2; // Reg[rt] + wire [31:0] alu_result =uut.mips.dp.alu_result; // ALU's output + wire [4:0] reg_writeaddr =uut.mips.dp.reg_writeaddr; // destination register + wire [31:0] reg_writedata =uut.mips.dp.reg_writedata; // write data for register file + wire [31:0] signImm =uut.mips.dp.signImm; // sign-/zero-extended immediate + wire [31:0] aluA =uut.mips.dp.aluA; // operand A for ALU + wire [31:0] aluB =uut.mips.dp.aluB; // operand B for ALU + + // Signals inside module uut.mips.c (controller) + wire [1:0] pcsel =uut.mips.c.pcsel; + wire [1:0] wasel =uut.mips.c.wasel; + wire sext =uut.mips.c.sext; + wire bsel =uut.mips.c.bsel; + wire [1:0] wdsel =uut.mips.c.wdsel; + wire wr =uut.mips.c.wr; + wire [1:0] asel =uut.mips.c.asel; + + // Display Wires + wire hsync, vsync; + wire [3:0] red, green, blue; + + // Instantiate the Unit Under Test (UUT) + top uut( + .clk(clk), .reset(reset), + .hsync(hsync), .vsync(vsync), + .red(red), .green(green), .blue(blue) + ); + + initial begin + // Initialize Inputs + clk = 0; + reset = 1; + end + + initial begin + #0.5 clk = 0; + forever + #0.5 clk = ~clk; + end + + initial begin + #50 $finish; + end + + + + // SELF-CHECKING CODE + + /*selfcheck c(); + + wire [31:0] c_pc=c.pc; + wire [31:0] c_instr=c.instr; + wire [31:0] c_mem_addr=c.mem_addr; + wire c_mem_wr=c.mem_wr; + wire [31:0] c_mem_readdata=c.mem_readdata; + wire [31:0] c_mem_writedata=c.mem_writedata; + wire c_werf=c.werf; + wire [4:0] c_alufn=c.alufn; + wire c_Z=c.Z; + wire [31:0] c_ReadData1=c.ReadData1; + wire [31:0] c_ReadData2=c.ReadData2; + wire [31:0] c_alu_result=c.alu_result; + wire [4:0] c_reg_writeaddr=c.reg_writeaddr; + wire [31:0] c_reg_writedata=c.reg_writedata; + wire [31:0] c_signImm=c.signImm; + wire [31:0] c_aluA=c.aluA; + wire [31:0] c_aluB=c.aluB; + wire [1:0] c_pcsel=c.pcsel; + wire [1:0] c_wasel=c.wasel; + wire c_sext=c.sext; + wire c_bsel=c.bsel; + wire [1:0] c_wdsel=c.wdsel; + wire c_wr=c.wr; + wire [1:0] c_asel=c.asel; + + + function mismatch; // some trickery needed to match two values with don't cares + input p, q; // mismatch in a bit position is ignored if q has an 'x' in that bit + integer p, q; + mismatch = (((p ^ q) ^ q) !== q); + endfunction + + wire ERROR = ERROR_pc | ERROR_instr | ERROR_mem_addr | ERROR_mem_wr | ERROR_mem_readdata + | ERROR_mem_writedata | ERROR_werf | ERROR_alufn | ERROR_Z + | ERROR_ReadData1 | ERROR_ReadData2 | ERROR_alu_result | ERROR_reg_writeaddr + | ERROR_reg_writedata | ERROR_signImm | ERROR_aluA | ERROR_aluB + | ERROR_pcsel | ERROR_wasel | ERROR_sext | ERROR_bsel | ERROR_wdsel | ERROR_wr | ERROR_asel; + + + wire ERROR_pc = mismatch(pc, c.pc) ? 1'bx : 1'b0; + wire ERROR_instr = mismatch(instr, c.instr) ? 1'bx : 1'b0; + wire ERROR_mem_addr = mismatch(mem_addr, c.mem_addr) ? 1'bx : 1'b0; + wire ERROR_mem_wr = mismatch(mem_wr, c.mem_wr) ? 1'bx : 1'b0; + wire ERROR_mem_readdata = mismatch(mem_readdata, c.mem_readdata) ? 1'bx : 1'b0; + wire ERROR_mem_writedata = c.mem_wr & (mismatch(mem_writedata, c.mem_writedata) ? 1'bx : 1'b0); + wire ERROR_werf = mismatch(werf, c.werf) ? 1'bx : 1'b0; + wire ERROR_alufn = mismatch(alufn, c.alufn) ? 1'bx : 1'b0; + wire ERROR_Z = mismatch(Z, c.Z) ? 1'bx : 1'b0; + wire ERROR_ReadData1 = mismatch(ReadData1, c.ReadData1) ? 1'bx : 1'b0; + wire ERROR_ReadData2 = mismatch(ReadData2, c.ReadData2) ? 1'bx : 1'b0; + wire ERROR_alu_result = mismatch(alu_result, c.alu_result) ? 1'bx : 1'b0; + wire ERROR_reg_writeaddr = c.werf & (mismatch(reg_writeaddr, c.reg_writeaddr) ? 1'bx : 1'b0); + wire ERROR_reg_writedata = c.werf & (mismatch(reg_writedata, c.reg_writedata) ? 1'bx : 1'b0); + wire ERROR_signImm = mismatch(signImm, c.signImm) ? 1'bx : 1'b0; + wire ERROR_aluA = mismatch(aluA, c.aluA) ? 1'bx : 1'b0; + wire ERROR_aluB = mismatch(aluB, c.aluB) ? 1'bx : 1'b0; + wire ERROR_pcsel = mismatch(pcsel, c.pcsel) ? 1'bx : 1'b0; + wire ERROR_wasel = c.werf & (mismatch(wasel, c.wasel) ? 1'bx : 1'b0); + wire ERROR_sext = mismatch(sext, c.sext) ? 1'bx : 1'b0; + wire ERROR_bsel = mismatch(bsel, c.bsel) ? 1'bx : 1'b0; + wire ERROR_wdsel = mismatch(wdsel, c.wdsel) ? 1'bx : 1'b0; + wire ERROR_wr = mismatch(wr, c.wr) ? 1'bx : 1'b0; + wire ERROR_asel = mismatch(asel, c.asel) ? 1'bx : 1'b0; + + + initial begin + $monitor("#%02d {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h%h, 32'h%h, 32'h%h, 1'b%b, 32'h%h, 32'h%h, 1'b%b, 5'b%b, 1'b%b, 32'h%h, 32'h%h, 32'h%h, 5'h%h, 32'h%h, 32'h%h, 32'h%h, 32'h%h, 2'b%b, 2'b%b, 1'b%b, 1'b%b, 2'b%b, 1'b%b, 2'b%b};", + $time, pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel); + end*/ + +endmodule + + + +// CHECKER MODULE +module selfcheck(); + reg [31:0] pc; + reg [31:0] instr; + reg [31:0] mem_addr; + reg mem_wr; + reg [31:0] mem_readdata; + reg [31:0] mem_writedata; + reg werf; + reg [4:0] alufn; + reg Z; + reg [31:0] ReadData1; + reg [31:0] ReadData2; + reg [31:0] alu_result; + reg [4:0] reg_writeaddr; + reg [31:0] reg_writedata; + reg [31:0] signImm; + reg [31:0] aluA; + reg [31:0] aluB; + reg [1:0] pcsel; + reg [1:0] wasel; + reg sext; + reg bsel; + reg [1:0] wdsel; + reg wr; + reg [1:0] asel; + +initial begin +fork +#00 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000000, 32'h201d003c, 32'h0000003c, 1'b0, 32'hxxxxxxxx, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h0000003c, 5'h1d, 32'h0000003c, 32'h0000003c, 32'h00000000, 32'h0000003c, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#01 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000004, 32'h8c040004, 32'h00000004, 1'b0, 32'h00000003, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h00000004, 5'h04, 32'h00000003, 32'h00000004, 32'h00000000, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#02 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000008, 32'h0c000005, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h0000000c, 32'h00000005, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#03 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'h23bdfff8, 32'h00000034, 1'b0, 32'hxxxxxxxx, 32'h0000003c, 1'b1, 5'b0xx01, 1'b0, 32'h0000003c, 32'h0000003c, 32'h00000034, 5'h1d, 32'h00000034, 32'hfffffff8, 32'h0000003c, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#04 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'hafbf0004, 32'h00000038, 1'b1, 32'hxxxxxxxx, 32'h0000000c, 1'b0, 5'b0xx01, 1'b0, 32'h00000034, 32'h0000000c, 32'h00000038, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h00000034, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#05 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hafa40000, 32'h00000034, 1'b1, 32'hxxxxxxxx, 32'h00000003, 1'b0, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000003, 32'h00000034, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00000034, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#06 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h28880002, 32'h00000000, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b1x011, 1'b1, 32'h00000003, 32'hxxxxxxxx, 32'h00000000, 5'h08, 32'h00000000, 32'h00000002, 32'h00000003, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#07 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h11000002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000000, 32'h00000000, 2'b01, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#08 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000030, 32'h2084ffff, 32'h00000002, 1'b0, 32'h00000000, 32'h00000003, 1'b1, 5'b0xx01, 1'b0, 32'h00000003, 32'h00000003, 32'h00000002, 5'h04, 32'h00000002, 32'hffffffff, 32'h00000003, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#09 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000034, 32'h0c000005, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h00000038, 32'h00000005, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#10 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'h23bdfff8, 32'h0000002c, 1'b0, 32'hxxxxxxxx, 32'h00000034, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000034, 32'h0000002c, 5'h1d, 32'h0000002c, 32'hfffffff8, 32'h00000034, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#11 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'hafbf0004, 32'h00000030, 1'b1, 32'hxxxxxxxx, 32'h00000038, 1'b0, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000038, 32'h00000030, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h0000002c, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#12 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hafa40000, 32'h0000002c, 1'b1, 32'hxxxxxxxx, 32'h00000002, 1'b0, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000002, 32'h0000002c, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h0000002c, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#13 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h28880002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b1x011, 1'b1, 32'h00000002, 32'h00000000, 32'h00000000, 5'h08, 32'h00000000, 32'h00000002, 32'h00000002, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#14 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h11000002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000000, 32'h00000000, 2'b01, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#15 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000030, 32'h2084ffff, 32'h00000001, 1'b0, 32'h00000000, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000002, 32'h00000002, 32'h00000001, 5'h04, 32'h00000001, 32'hffffffff, 32'h00000002, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#16 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000034, 32'h0c000005, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h00000038, 32'h00000005, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#17 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'h23bdfff8, 32'h00000024, 1'b0, 32'hxxxxxxxx, 32'h0000002c, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h0000002c, 32'h00000024, 5'h1d, 32'h00000024, 32'hfffffff8, 32'h0000002c, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#18 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'hafbf0004, 32'h00000028, 1'b1, 32'hxxxxxxxx, 32'h00000038, 1'b0, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000038, 32'h00000028, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h00000024, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#19 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hafa40000, 32'h00000024, 1'b1, 32'hxxxxxxxx, 32'h00000001, 1'b0, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000001, 32'h00000024, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00000024, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#20 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h28880002, 32'h00000001, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b1x011, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'h08, 32'h00000001, 32'h00000002, 32'h00000001, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#21 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h11000002, 32'h00000001, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000001, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#22 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000028, 32'h00041020, 32'h00000001, 1'b0, 32'h00000000, 32'h00000001, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000001, 32'h00000001, 5'h02, 32'h00000001, 32'h00001020, 32'h00000000, 32'h00000001, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#23 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000002c, 32'h08000012, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000012, 32'hxxxxxxxx, 32'h000000XX, 2'b10, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#24 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h8fbf0004, 32'h00000028, 1'b0, 32'h00000038, 32'h00000038, 1'b1, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000038, 32'h00000028, 5'h1f, 32'h00000038, 32'h00000004, 32'h00000024, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#25 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h23bd0008, 32'h0000002c, 1'b0, 32'h00000002, 32'h00000024, 1'b1, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000024, 32'h0000002c, 5'h1d, 32'h0000002c, 32'h00000008, 32'h00000024, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#26 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000050, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000038, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#27 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000038, 32'h8fa40000, 32'h0000002c, 1'b0, 32'h00000002, 32'h00000001, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000001, 32'h0000002c, 5'h04, 32'h00000002, 32'h00000000, 32'h0000002c, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#28 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000003c, 32'h00441020, 32'h00000003, 1'b0, 32'h00000000, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000001, 32'h00000002, 32'h00000003, 5'h02, 32'h00000003, 32'h00001020, 32'h00000001, 32'h00000002, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#29 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000040, 32'h00441020, 32'h00000005, 1'b0, 32'h00000003, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000003, 32'h00000002, 32'h00000005, 5'h02, 32'h00000005, 32'h00001020, 32'h00000003, 32'h00000002, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#30 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000044, 32'h2042ffff, 32'h00000004, 1'b0, 32'h00000003, 32'h00000005, 1'b1, 5'b0xx01, 1'b0, 32'h00000005, 32'h00000005, 32'h00000004, 5'h02, 32'h00000004, 32'hffffffff, 32'h00000005, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#31 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h8fbf0004, 32'h00000030, 1'b0, 32'h00000038, 32'h00000038, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000038, 32'h00000030, 5'h1f, 32'h00000038, 32'h00000004, 32'h0000002c, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#32 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h23bd0008, 32'h00000034, 1'b0, 32'h00000003, 32'h0000002c, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h0000002c, 32'h00000034, 5'h1d, 32'h00000034, 32'h00000008, 32'h0000002c, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#33 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000050, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000038, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#34 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000038, 32'h8fa40000, 32'h00000034, 1'b0, 32'h00000003, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000002, 32'h00000034, 5'h04, 32'h00000003, 32'h00000000, 32'h00000034, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#35 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000003c, 32'h00441020, 32'h00000007, 1'b0, 32'h00000003, 32'h00000003, 1'b1, 5'b0xx01, 1'b0, 32'h00000004, 32'h00000003, 32'h00000007, 5'h02, 32'h00000007, 32'h00001020, 32'h00000004, 32'h00000003, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#36 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000040, 32'h00441020, 32'h0000000a, 1'b0, 32'hxxxxxxxx, 32'h00000003, 1'b1, 5'b0xx01, 1'b0, 32'h00000007, 32'h00000003, 32'h0000000a, 5'h02, 32'h0000000a, 32'h00001020, 32'h00000007, 32'h00000003, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#37 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000044, 32'h2042ffff, 32'h00000009, 1'b0, 32'hxxxxxxxx, 32'h0000000a, 1'b1, 5'b0xx01, 1'b0, 32'h0000000a, 32'h0000000a, 32'h00000009, 5'h02, 32'h00000009, 32'hffffffff, 32'h0000000a, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#38 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h8fbf0004, 32'h00000038, 1'b0, 32'h0000000c, 32'h00000038, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000038, 32'h00000038, 5'h1f, 32'h0000000c, 32'h00000004, 32'h00000034, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#39 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h23bd0008, 32'h0000003c, 1'b0, 32'hxxxxxxxx, 32'h00000034, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000034, 32'h0000003c, 5'h1d, 32'h0000003c, 32'h00000008, 32'h00000034, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#40 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000050, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h0000000c, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#41 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000000c, 32'hac020000, 32'h00000000, 1'b1, 32'h00000000, 32'h00000009, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000009, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00000000, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#42 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000010, 32'h08000004, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +join +end + +endmodule diff --git a/Project.sim/sim_1/behav/Project_screentest_nopause.sv b/Project.sim/sim_1/behav/Project_screentest_nopause.sv new file mode 100644 index 0000000..f818212 --- /dev/null +++ b/Project.sim/sim_1/behav/Project_screentest_nopause.sv @@ -0,0 +1,308 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 4/15/2015 +// +// PLEASE README! +// ============== +// +// This is a self-checking tester for your full MIPS processor +// plus memory-mapped IO. +// +// Use this tester carefully! The names of your top-level input/output +// and internal signals may be different, so modify all of signal names on the +// right-hand-side of the "wire" assigments appearing above the uut +// instantiation. Observe that the uut itself only has clock and reset inputs +// now, and no debug outputs. Also, the parameters specifying the names of the +// memory initialization files must match the actual file names. +// +// If you decide not to use some of these internal signals for debugging, you +// may comment the relevant lines out. Be sure to comment out the +// corresponding "ERROR_*" lines below as well. +// +// Finally, note that in my bitmap memory, each 12-bit color is encoded as +// RRRRGGGGBBBB (i.e., red is most significant). If you have chosen a different +// order for the red/green/blue color values, you may see ERROR signals for the +// colors light up, but there is no error if you are consistent with your +// RGB ordering. +// +////////////////////////////////////////////////////////////////////////////////// + + +module project_screentest; + + // Inputs + reg clk; + reg reset; + + // Signals inside top-level module uut + wire [31:0] pc =uut.pc; // PC + wire [31:0] instr =uut.instr; // instr coming out of instr mem + wire [31:0] mem_addr =uut.mem_addr; // addr sent to data mem + wire mem_wr =uut.mem_wr; // write enable for data mem + wire [31:0] mem_readdata =uut.mem_readdata; // data read from data mem + wire [31:0] mem_writedata =uut.mem_writedata; // write data for data mem + + // Signals inside module uut.mips + wire werf =uut.mips.werf; // WERF = write enable for register file + wire [4:0] alufn =uut.mips.alufn; // ALU function + wire Z =uut.mips.Z; // Zero flag + + // Signals inside module uut.mips.dp (datapath) + wire [31:0] ReadData1 =uut.mips.dp.ReadData1; // Reg[rs] + wire [31:0] ReadData2 =uut.mips.dp.ReadData2; // Reg[rt] + wire [31:0] alu_result =uut.mips.dp.alu_result; // ALU's output + wire [4:0] reg_writeaddr =uut.mips.dp.reg_writeaddr; // destination register + wire [31:0] reg_writedata =uut.mips.dp.reg_writedata; // write data for register file + wire [31:0] signImm =uut.mips.dp.signImm; // sign-/zero-extended immediate + wire [31:0] aluA =uut.mips.dp.aluA; // operand A for ALU + wire [31:0] aluB =uut.mips.dp.aluB; // operand B for ALU + + // Signals inside module uut.mips.c (controller) + wire [1:0] pcsel =uut.mips.c.pcsel; + wire [1:0] wasel =uut.mips.c.wasel; + wire sext =uut.mips.c.sext; + wire bsel =uut.mips.c.bsel; + wire [1:0] wdsel =uut.mips.c.wdsel; + wire wr =uut.mips.c.wr; + wire [1:0] asel =uut.mips.c.asel; + + // Signals related to module memIO (memory + memory-mapped IO) + wire [10:0] smem_addr =uut.smem_addr; // address from vgadisplaydriver to access screen mem + wire [3:0] charcode =uut.charcode; // character code returned by screen mem + wire dmem_wr =uut.memIO.dmem_wr; + wire smem_wr =uut.memIO.smem_wr; + + // Signals related to module vgadisplaydriver (display driver) + wire hsync =uut.hsync; + wire vsync =uut.vsync; + wire [3:0] red =uut.red; + wire [3:0] green =uut.green; + wire [3:0] blue =uut.blue; + wire [9:0] x =uut.displaydriver.x; + wire [9:0] y =uut.displaydriver.y; + wire [11:0] bmem_addr =uut.displaydriver.bitmapAddr; + wire [11:0] bmem_color =uut.displaydriver.colorValue; + + + // Instantiate the Unit Under Test (UUT) + top #("imem.txt", "dmem.txt", "smem.txt", "bmem.txt") uut( + .clk(clk), + .reset(reset) + ); + +// +// CHECK ALL VALUES ABOVE THIS LINE +// YOU SHOULD NOT NEED TO MODIFY ANYTHING BELOW +// + + initial begin + // Initialize Inputs + clk = 0; + reset = 1; + end + + initial begin + #0.5 clk = 0; + forever + #0.5 clk = ~clk; + end + + initial begin + #50 $finish; + end + + + + // SELF-CHECKING CODE + + selfcheck c(); + + wire [31:0] c_pc=c.pc; + wire [31:0] c_instr=c.instr; + wire [31:0] c_mem_addr=c.mem_addr; + wire c_mem_wr=c.mem_wr; + wire [31:0] c_mem_readdata=c.mem_readdata; + wire [31:0] c_mem_writedata=c.mem_writedata; + wire c_werf=c.werf; + wire [4:0] c_alufn=c.alufn; + wire c_Z=c.Z; + wire [31:0] c_ReadData1=c.ReadData1; + wire [31:0] c_ReadData2=c.ReadData2; + wire [31:0] c_alu_result=c.alu_result; + wire [4:0] c_reg_writeaddr=c.reg_writeaddr; + wire [31:0] c_reg_writedata=c.reg_writedata; + wire [31:0] c_signImm=c.signImm; + wire [31:0] c_aluA=c.aluA; + wire [31:0] c_aluB=c.aluB; + wire [1:0] c_pcsel=c.pcsel; + wire [1:0] c_wasel=c.wasel; + wire c_sext=c.sext; + wire c_bsel=c.bsel; + wire [1:0] c_wdsel=c.wdsel; + wire c_wr=c.wr; + wire [1:0] c_asel=c.asel; + wire [10:0] c_smem_addr=c.smem_addr; + wire [3:0] c_charcode=c.charcode; + wire c_dmem_wr=c.dmem_wr; + wire c_smem_wr=c.smem_wr; + wire c_hsync=c.hsync; + wire c_vsync=c.vsync; + wire [3:0] c_red=c.red; + wire [3:0] c_green=c.green; + wire [3:0] c_blue=c.blue; + wire [9:0] c_x=c.x; + wire [9:0] c_y=c.x; + wire [11:0] c_bmem_addr=c.bmem_addr; + wire [11:0] c_bmem_color=c.bmem_color; + + + function mismatch; // some trickery needed to match two values with don't cares + input p, q; // mismatch in a bit position is ignored if q has an 'x' in that bit + integer p, q; + mismatch = (((p ^ q) ^ q) !== q); + endfunction + + wire ERROR = ERROR_pc | ERROR_instr | ERROR_mem_addr | ERROR_mem_wr | ERROR_mem_readdata + | ERROR_mem_writedata | ERROR_werf | ERROR_alufn | ERROR_Z + | ERROR_ReadData1 | ERROR_ReadData2 | ERROR_alu_result | ERROR_reg_writeaddr + | ERROR_reg_writedata | ERROR_signImm | ERROR_aluA | ERROR_aluB + | ERROR_pcsel | ERROR_wasel | ERROR_sext | ERROR_bsel | ERROR_wdsel | ERROR_wr | ERROR_asel + | ERROR_smem_addr | ERROR_charcode | ERROR_dmem_wr | ERROR_smem_wr | ERROR_hsync | ERROR_vsync + | ERROR_red | ERROR_green | ERROR_blue | ERROR_x | ERROR_y | ERROR_bmem_addr | ERROR_bmem_color; + + + wire ERROR_pc = mismatch(pc, c.pc) ? 1'bx : 1'b0; + wire ERROR_instr = mismatch(instr, c.instr) ? 1'bx : 1'b0; + wire ERROR_mem_addr = mismatch(mem_addr, c.mem_addr) ? 1'bx : 1'b0; + wire ERROR_mem_wr = mismatch(mem_wr, c.mem_wr) ? 1'bx : 1'b0; + wire ERROR_mem_readdata = mismatch(mem_readdata, c.mem_readdata) ? 1'bx : 1'b0; + wire ERROR_mem_writedata = c.mem_wr & (mismatch(mem_writedata, c.mem_writedata) ? 1'bx : 1'b0); + wire ERROR_werf = mismatch(werf, c.werf) ? 1'bx : 1'b0; + wire ERROR_alufn = mismatch(alufn, c.alufn) ? 1'bx : 1'b0; + wire ERROR_Z = mismatch(Z, c.Z) ? 1'bx : 1'b0; + wire ERROR_ReadData1 = mismatch(ReadData1, c.ReadData1) ? 1'bx : 1'b0; + wire ERROR_ReadData2 = mismatch(ReadData2, c.ReadData2) ? 1'bx : 1'b0; + wire ERROR_alu_result = mismatch(alu_result, c.alu_result) ? 1'bx : 1'b0; + wire ERROR_reg_writeaddr = c.werf & (mismatch(reg_writeaddr, c.reg_writeaddr) ? 1'bx : 1'b0); + wire ERROR_reg_writedata = c.werf & (mismatch(reg_writedata, c.reg_writedata) ? 1'bx : 1'b0); + wire ERROR_signImm = mismatch(signImm, c.signImm) ? 1'bx : 1'b0; + wire ERROR_aluA = mismatch(aluA, c.aluA) ? 1'bx : 1'b0; + wire ERROR_aluB = mismatch(aluB, c.aluB) ? 1'bx : 1'b0; + wire ERROR_pcsel = mismatch(pcsel, c.pcsel) ? 1'bx : 1'b0; + wire ERROR_wasel = c.werf & (mismatch(wasel, c.wasel) ? 1'bx : 1'b0); + wire ERROR_sext = mismatch(sext, c.sext) ? 1'bx : 1'b0; + wire ERROR_bsel = mismatch(bsel, c.bsel) ? 1'bx : 1'b0; + wire ERROR_wdsel = mismatch(wdsel, c.wdsel) ? 1'bx : 1'b0; + wire ERROR_wr = mismatch(wr, c.wr) ? 1'bx : 1'b0; + wire ERROR_asel = mismatch(asel, c.asel) ? 1'bx : 1'b0; + wire ERROR_smem_addr = mismatch(smem_addr, c.smem_addr) ? 1'bx : 1'b0; + wire ERROR_charcode = mismatch(charcode, c.charcode) ? 1'bx : 1'b0; + wire ERROR_dmem_wr = mismatch(dmem_wr, c.dmem_wr) ? 1'bx : 1'b0; + wire ERROR_smem_wr = mismatch(smem_wr, c.smem_wr) ? 1'bx : 1'b0; + wire ERROR_hsync = mismatch(hsync, c.hsync) ? 1'bx : 1'b0; + wire ERROR_vsync = mismatch(vsync, c.vsync) ? 1'bx : 1'b0; + wire ERROR_red = mismatch(red, c.red) ? 1'bx : 1'b0; + wire ERROR_green = mismatch(green, c.green) ? 1'bx : 1'b0; + wire ERROR_blue = mismatch(blue, c.blue) ? 1'bx : 1'b0; + wire ERROR_x = mismatch(x, c.x) ? 1'bx : 1'b0; + wire ERROR_y = mismatch(y, c.y) ? 1'bx : 1'b0; + wire ERROR_bmem_addr = mismatch(bmem_addr, c.bmem_addr) ? 1'bx : 1'b0; + wire ERROR_bmem_color = mismatch(bmem_color, c.bmem_color) ? 1'bx : 1'b0; + + //initial begin + // $monitor("#%02d {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h%h, 32'h%h, 32'h%h, 1'b%b, 32'h%h, 32'h%h, 1'b%b, 5'b%b, 1'b%b, 32'h%h, 32'h%h, 32'h%h, 5'h%h, 32'h%h, 32'h%h, 32'h%h, 32'h%h, 2'b%b, 2'b%b, 1'b%b, 1'b%b, 2'b%b, 1'b%b, 2'b%b};", + // $time, pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel); + // $monitor("#%02d {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h%h, 4'h%h, 1'b%b, 1'b%b, 1'b%b, 1'b%b, 4'h%h, 4'h%h, 4'h%h, 10'h%h, 10'h%h, 12'h%h, 12'h%h};", + // $time, smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color); + //end + +endmodule + + + +// CHECKER MODULE +module selfcheck(); + reg [31:0] pc; + reg [31:0] instr; + reg [31:0] mem_addr; + reg mem_wr; + reg [31:0] mem_readdata; + reg [31:0] mem_writedata; + reg werf; + reg [4:0] alufn; + reg Z; + reg [31:0] ReadData1; + reg [31:0] ReadData2; + reg [31:0] alu_result; + reg [4:0] reg_writeaddr; + reg [31:0] reg_writedata; + reg [31:0] signImm; + reg [31:0] aluA; + reg [31:0] aluB; + reg [1:0] pcsel; + reg [1:0] wasel; + reg sext; + reg bsel; + reg [1:0] wdsel; + reg wr; + reg [1:0] asel; + reg [10:0] smem_addr; + reg [3:0] charcode; + reg dmem_wr; + reg smem_wr; + reg hsync; + reg vsync; + reg [3:0] red; + reg [3:0] green; + reg [3:0] blue; + reg [9:0] x; + reg [9:0] y; + reg [11:0] bmem_addr; + reg [11:0] bmem_color; + +initial begin +fork + +#00 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000000, 32'h00000020, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'h00, 32'h00000000, 32'h00000020, 32'h00000000, 32'h00000000, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#00 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h000, 10'h000, 12'h000, 12'hf00}; +#01 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000004, 32'h201d203c, 32'h0000203c, 1'b0, 32'hxxxxxxxx, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h0000203c, 5'h1d, 32'h0000203c, 32'h0000203c, 32'h00000000, 32'h0000203c, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#02 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000008, 32'h20040000, 32'h00000000, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b1, 32'h00000000, 32'hxxxxxxxx, 32'h00000000, 5'h04, 32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#03 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000000c, 32'h0c000009, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h00000010, 32'h00000009, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#04 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h23bdfff8, 32'h00002034, 1'b0, 32'hxxxxxxxx, 32'h0000203c, 1'b1, 5'b0xx01, 1'b0, 32'h0000203c, 32'h0000203c, 32'h00002034, 5'h1d, 32'h00002034, 32'hfffffff8, 32'h0000203c, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#04 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#05 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000028, 32'hafbf0004, 32'h00002038, 1'b1, 32'hxxxxxxxx, 32'h00000010, 1'b0, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000010, 32'h00002038, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h00002034, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#05 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b1, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#06 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000002c, 32'hafa40000, 32'h00002034, 1'b1, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000000, 32'h00002034, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00002034, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#07 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000030, 32'h00042400, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'bx0010, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'h04, 32'h00000000, 32'h00002400, 32'h00000010, 32'h00000000, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b01}; +#07 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#08 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h002, 10'h000, 12'h002, 12'hf00}; +#08 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000034, 32'h10800002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000000, 32'h00000000, 2'b01, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#09 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000040, 32'h8fa40000, 32'h00002034, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000000, 32'h00002034, 5'h04, 32'h00000000, 32'h00000000, 32'h00002034, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#10 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000044, 32'h8fbf0004, 32'h00002038, 1'b0, 32'h00000010, 32'h00000010, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000010, 32'h00002038, 5'h1f, 32'h00000010, 32'h00000004, 32'h00002034, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#11 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h23bd0008, 32'h0000203c, 1'b0, 32'hxxxxxxxx, 32'h00002034, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00002034, 32'h0000203c, 5'h1d, 32'h0000203c, 32'h00000008, 32'h00002034, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#12 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000010, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#12 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h003, 10'h000, 12'h003, 12'hf00}; +#13 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000010, 32'h20080002, 32'h00000002, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h00000002, 5'h08, 32'h00000002, 32'h00000002, 32'h00000000, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#14 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'hac084000, 32'h00004000, 1'b1, 32'h00000000, 32'h00000002, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000002, 32'h00004000, 5'hxx, 32'hxxxxxxxx, 32'h00004000, 32'h00000000, 32'h00004000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#14 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b1, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h003, 10'h000, 12'h003, 12'hf00}; +#15 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'h20080003, 32'h00000003, 1'b0, 32'h00000000, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000002, 32'h00000003, 5'h08, 32'h00000003, 32'h00000003, 32'h00000000, 32'h00000003, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#15 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h003, 10'h000, 12'h203, 12'h00f}; +#16 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hac084001, 32'h00004001, 1'b1, 32'h00000001, 32'h00000003, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000003, 32'h00004001, 5'hxx, 32'hxxxxxxxx, 32'h00004001, 32'h00000000, 32'h00004001, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#16 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b1, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h004, 10'h000, 12'h204, 12'h00f}; +#17 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h08000008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#17 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h004, 10'h000, 12'h204, 12'h00f}; +#20 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h005, 10'h000, 12'h205, 12'h00f}; +#24 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h006, 10'h000, 12'h206, 12'h00f}; +#28 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h007, 10'h000, 12'h207, 12'h00f}; +#32 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h008, 10'h000, 12'h208, 12'h00f}; +#36 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h009, 10'h000, 12'h209, 12'h00f}; +#40 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00a, 10'h000, 12'h20a, 12'h00f}; +#44 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00b, 10'h000, 12'h20b, 12'h00f}; +#48 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00c, 10'h000, 12'h20c, 12'h00f}; + +join +end + +endmodule \ No newline at end of file diff --git a/Project.sim/sim_1/behav/bmem_init.txt b/Project.sim/sim_1/behav/bmem_init.txt new file mode 100644 index 0000000..4981092 --- /dev/null +++ b/Project.sim/sim_1/behav/bmem_init.txt @@ -0,0 +1,1024 @@ +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff \ No newline at end of file diff --git a/Project.sim/sim_1/behav/compile.bat b/Project.sim/sim_1/behav/compile.bat new file mode 100644 index 0000000..f662848 --- /dev/null +++ b/Project.sim/sim_1/behav/compile.bat @@ -0,0 +1,10 @@ +@echo off +set xv_path=C:\\Xilinx\\Vivado\\2014.4\\bin +echo "xvlog -m64 -prj project_screentest_vlog.prj" +call %xv_path%/xvlog -m64 -prj project_screentest_vlog.prj -log compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/Project.sim/sim_1/behav/compile.log b/Project.sim/sim_1/behav/compile.log new file mode 100644 index 0000000..9c5301a --- /dev/null +++ b/Project.sim/sim_1/behav/compile.log @@ -0,0 +1,63 @@ +Determining compilation order of HDL files. +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module fulladder +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module adder +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module comparator +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module addsub +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module logical +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module shifter +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ALU +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module signExtension +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module xycounter +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module register_file +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module vgatimer +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module smem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module controller +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module bitmapmem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module dmem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module datapath +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/clockdiv.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module clockdivider_Nexys4 +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module debouncer +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module vgadisplaydriver +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module imem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module memIO +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module mips +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/imports/src/Lab10_test_sqr.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module mips_test_sqr +INFO: [VRFC 10-311] analyzing module selfcheck +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module project_screentest +WARNING: [VRFC 10-756] identifier ERROR_pc is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:167] +WARNING: [VRFC 10-756] identifier ERROR_mem_writedata is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:168] +WARNING: [VRFC 10-756] identifier ERROR_ReadData1 is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:169] +WARNING: [VRFC 10-756] identifier ERROR_reg_writedata is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:170] +WARNING: [VRFC 10-756] identifier ERROR_pcsel is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:171] +WARNING: [VRFC 10-756] identifier ERROR_smem_addr is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:172] +WARNING: [VRFC 10-756] identifier ERROR_red is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:173] +INFO: [VRFC 10-311] analyzing module selfcheck +WARNING: [VRFC 10-1195] overwriting previous definition of module selfcheck [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:226] +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav/glbl.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module glbl diff --git a/Project.sim/sim_1/behav/dmem_init.txt b/Project.sim/sim_1/behav/dmem_init.txt new file mode 100644 index 0000000..72cf8de --- /dev/null +++ b/Project.sim/sim_1/behav/dmem_init.txt @@ -0,0 +1 @@ +0 // data memory not used in this program \ No newline at end of file diff --git a/Project.sim/sim_1/behav/elaborate.bat b/Project.sim/sim_1/behav/elaborate.bat new file mode 100644 index 0000000..b8b0057 --- /dev/null +++ b/Project.sim/sim_1/behav/elaborate.bat @@ -0,0 +1,9 @@ +@echo off +set xv_path=C:\\Xilinx\\Vivado\\2014.4\\bin +call %xv_path%/xelab -wto 5f5d7ddd32cb4c0cb289603e426c9fed -m64 --debug typical --relax -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot project_screentest_behav xil_defaultlib.project_screentest xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/Project.sim/sim_1/behav/elaborate.log b/Project.sim/sim_1/behav/elaborate.log new file mode 100644 index 0000000..75f296e --- /dev/null +++ b/Project.sim/sim_1/behav/elaborate.log @@ -0,0 +1,12 @@ +Vivado Simulator 2014.4 +Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2014.4/bin/unwrapped/win64.o/xelab.exe -wto 5f5d7ddd32cb4c0cb289603e426c9fed --debug typical --relax -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot project_screentest_behav xil_defaultlib.project_screentest xil_defaultlib.glbl -log elaborate.log +Multi-threading is on. Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-1459] too many parameters for module instance uut [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:90] +ERROR: [VRFC 10-93] smem_addr is not declared under prefix uut [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:72] +ERROR: [VRFC 10-93] dmem_wr is not declared under prefix memIO [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:74] +ERROR: [VRFC 10-93] smem_wr is not declared under prefix memIO [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/new/Project_screentest_nopause.sv:75] +WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port WriteAddr [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:88] +WARNING: [VRFC 10-278] actual bit length 1 differs from formal bit length 8 for port charCode [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v:89] +ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. diff --git a/Project.sim/sim_1/behav/glbl.v b/Project.sim/sim_1/behav/glbl.v new file mode 100644 index 0000000..2edbf14 --- /dev/null +++ b/Project.sim/sim_1/behav/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Project.sim/sim_1/behav/imem_init.txt b/Project.sim/sim_1/behav/imem_init.txt new file mode 100644 index 0000000..9ffd400 --- /dev/null +++ b/Project.sim/sim_1/behav/imem_init.txt @@ -0,0 +1,7 @@ +00000020 +201d203c +20080002 +ac084000 +20080003 +ac084001 +08000006 \ No newline at end of file diff --git a/Project.sim/sim_1/behav/mips_test_sqr_behav.wdb b/Project.sim/sim_1/behav/mips_test_sqr_behav.wdb new file mode 100644 index 0000000..bb2e29f Binary files /dev/null and b/Project.sim/sim_1/behav/mips_test_sqr_behav.wdb differ diff --git a/Project.sim/sim_1/behav/project_screentest_vlog.prj b/Project.sim/sim_1/behav/project_screentest_vlog.prj new file mode 100644 index 0000000..cf8e03d --- /dev/null +++ b/Project.sim/sim_1/behav/project_screentest_vlog.prj @@ -0,0 +1,29 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/fulladder.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/adder.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/comparator.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/addsub.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/logical.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/shifter.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/alu.v" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/signExtension.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/xycounter.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/register_file.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/vgatimer.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/smem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/controller.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/bitmapmem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/dmem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/datapath.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/clockdiv.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/debouncer.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/vgadisplaydriver.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/imem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/memIO.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/mips.sv" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/top.v" +sv xil_defaultlib "../../../Project.srcs/sim_1/imports/src/Lab10_test_sqr.sv" +sv xil_defaultlib "../../../Project.srcs/sim_1/new/Project_screentest_nopause.sv" + +# compile glbl module +verilog xil_defaultlib "glbl.v" diff --git a/Project.sim/sim_1/behav/regd_init.txt b/Project.sim/sim_1/behav/regd_init.txt new file mode 100644 index 0000000..463fdf1 --- /dev/null +++ b/Project.sim/sim_1/behav/regd_init.txt @@ -0,0 +1,32 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 \ No newline at end of file diff --git a/Project.sim/sim_1/behav/simulate.log b/Project.sim/sim_1/behav/simulate.log new file mode 100644 index 0000000..73a38c4 --- /dev/null +++ b/Project.sim/sim_1/behav/simulate.log @@ -0,0 +1,5 @@ +Vivado Simulator 2014.4 +Time resolution is 1 ps +WARNING: File smem_init.txt referenced on C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. +WARNING: File dmem_init.txt referenced on C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv at line 27 cannot be opened for reading. Please ensure that this file is available in the current working directory. +$finish called at time : 50 ns : File "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_1/imports/src/Lab10_test_sqr.sv" Line 88 diff --git a/Project.sim/sim_1/behav/smem_init.txt b/Project.sim/sim_1/behav/smem_init.txt new file mode 100644 index 0000000..97a86c8 --- /dev/null +++ b/Project.sim/sim_1/behav/smem_init.txt @@ -0,0 +1,1200 @@ +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +00 +01 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 +03 +02 \ No newline at end of file diff --git a/Project.sim/sim_1/behav/webtalk.jou b/Project.sim/sim_1/behav/webtalk.jou new file mode 100644 index 0000000..82d5ea1 --- /dev/null +++ b/Project.sim/sim_1/behav/webtalk.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Webtalk v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Thu Apr 16 01:39:37 2015 +# Process ID: 6968 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav/webtalk.log +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav\webtalk.jou +#----------------------------------------------------------- +source C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Project.sim/sim_1/behav/webtalk.log b/Project.sim/sim_1/behav/webtalk.log new file mode 100644 index 0000000..a29508e --- /dev/null +++ b/Project.sim/sim_1/behav/webtalk.log @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Thu Apr 16 01:39:37 2015 +# Process ID: 6968 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav/webtalk.log +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav\webtalk.jou +#----------------------------------------------------------- +source C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-186] 'C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Apr 16 01:39:40 2015. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2014.4/doc/webtalk_introduction.html. +INFO: [Common 17-206] Exiting Webtalk at Thu Apr 16 01:39:40 2015... diff --git a/Project.sim/sim_1/behav/xelab.pb b/Project.sim/sim_1/behav/xelab.pb new file mode 100644 index 0000000..022cf90 Binary files /dev/null and b/Project.sim/sim_1/behav/xelab.pb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/.xsim_webtallk.info b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..40e8441 --- /dev/null +++ b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +0 +1429162775 +2 +0 +4b51deaa-697c-410c-b49d-3967bd814bfe diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/usage_statistics_ext_xsim.html b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..2b9068d --- /dev/null +++ b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,54 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
date_generatedThu Apr 16 01:39:35 2015product_versionXSIM v2014.4 (64-bit)
build_version1071353os_platformWIN64
registration_id210990371_0_0_454tool_flowxsim
betaFALSEroute_designFALSE
target_familynot_applicabletarget_devicenot_applicable
target_packagenot_applicabletarget_speednot_applicable
random_idcbe99d29-70fc-410f-b2e1-f5330b3232ceproject_id4b51deaa-697c-410c-b49d-3967bd814bfe
project_iteration1

+ + + + + + + + +
user_environment
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
cpu_nameIntel(R) Core(TM) i5-3320M CPU @ 2.60GHzcpu_speed2594 MHz
total_processors1system_ram3.000 GB

+ + +
vivado_usage

+ + + + +
xsim
+ + + + +
command_line_options
command=xsimrunall=false
+
+ + + + + + + +
usage
trace_waveform=trueruntime=50 nsiteration=0simulation_time=0.14_sec
simulation_memory=17964_KB
+

+ + diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/usage_statistics_ext_xsim.xml b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..841e3bd --- /dev/null +++ b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,45 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ + +
+
+ + + + + +
+
+
+ diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.mem b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.mem new file mode 100644 index 0000000..c5b65bc Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.mem differ diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.type b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.type new file mode 100644 index 0000000..14a09a2 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.type differ diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.xdbg b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.xdbg new file mode 100644 index 0000000..d05049c Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsim.xdbg differ diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimcrash.log b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimk.exe b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimk.exe new file mode 100644 index 0000000..f284b6f Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimk.exe differ diff --git a/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimkernel.log b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimkernel.log new file mode 100644 index 0000000..01e41d3 --- /dev/null +++ b/Project.sim/sim_1/behav/xsim.dir/mips_test_sqr_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/mips_test_sqr_behav/xsimk.exe -simmode gui -wdb mips_test_sqr_behav.wdb -simrunnum 0 -socket 50537 +Design successfully loaded +Design Loading Memory Usage: 17516 KB (Peak: 17516 KB) +Design Loading CPU Usage: 124 ms +Simulation completed +Simulation Memory Usage: 17964 KB (Peak: 17964 KB) +Simulation CPU Usage: 140 ms diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/@a@l@u.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/@a@l@u.sdb new file mode 100644 index 0000000..54444cc Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/@a@l@u.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/adder.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/adder.sdb new file mode 100644 index 0000000..5447df5 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/adder.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/addsub.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/addsub.sdb new file mode 100644 index 0000000..ae1a3f2 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/addsub.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/bitmapmem.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/bitmapmem.sdb new file mode 100644 index 0000000..7160cb5 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/bitmapmem.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/clockdivider_@nexys4.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/clockdivider_@nexys4.sdb new file mode 100644 index 0000000..a6339fb Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/clockdivider_@nexys4.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/comparator.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/comparator.sdb new file mode 100644 index 0000000..8cf44d2 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/comparator.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/controller.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/controller.sdb new file mode 100644 index 0000000..816a2c2 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/controller.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/datapath.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/datapath.sdb new file mode 100644 index 0000000..a087ba5 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/datapath.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/debouncer.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/debouncer.sdb new file mode 100644 index 0000000..3fdbc37 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/debouncer.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/dmem.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/dmem.sdb new file mode 100644 index 0000000..ffdda9a Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/dmem.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/fulladder.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/fulladder.sdb new file mode 100644 index 0000000..1ca4588 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/fulladder.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/glbl.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/glbl.sdb new file mode 100644 index 0000000..2074ee5 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/glbl.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/imem.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/imem.sdb new file mode 100644 index 0000000..d55877c Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/imem.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/logical.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/logical.sdb new file mode 100644 index 0000000..a3ec403 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/logical.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mem@i@o.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mem@i@o.sdb new file mode 100644 index 0000000..0d49f9e Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mem@i@o.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mips.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mips.sdb new file mode 100644 index 0000000..9462190 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mips.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mips_test_sqr.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mips_test_sqr.sdb new file mode 100644 index 0000000..2f286df Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/mips_test_sqr.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/project_screentest.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/project_screentest.sdb new file mode 100644 index 0000000..947f8e5 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/project_screentest.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/register_file.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/register_file.sdb new file mode 100644 index 0000000..5147cc1 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/register_file.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/selfcheck.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/selfcheck.sdb new file mode 100644 index 0000000..7554655 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/selfcheck.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/shifter.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/shifter.sdb new file mode 100644 index 0000000..954a507 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/shifter.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/sign@extension.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/sign@extension.sdb new file mode 100644 index 0000000..fcedecb Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/sign@extension.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/smem.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/smem.sdb new file mode 100644 index 0000000..3e71dc0 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/smem.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/top.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/top.sdb new file mode 100644 index 0000000..8e39976 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/top.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/vgadisplaydriver.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/vgadisplaydriver.sdb new file mode 100644 index 0000000..cd4aee2 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/vgadisplaydriver.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/vgatimer.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/vgatimer.sdb new file mode 100644 index 0000000..4d4f2aa Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/vgatimer.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/xycounter.sdb b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/xycounter.sdb new file mode 100644 index 0000000..f29c7a4 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xil_defaultlib/xycounter.sdb differ diff --git a/Project.sim/sim_1/behav/xsim.dir/xsim.svtype b/Project.sim/sim_1/behav/xsim.dir/xsim.svtype new file mode 100644 index 0000000..5142c79 Binary files /dev/null and b/Project.sim/sim_1/behav/xsim.dir/xsim.svtype differ diff --git a/Project.sim/sim_1/behav/xvlog.pb b/Project.sim/sim_1/behav/xvlog.pb new file mode 100644 index 0000000..28b86aa Binary files /dev/null and b/Project.sim/sim_1/behav/xvlog.pb differ diff --git a/Project.sim/sim_2/behav/Project_screentest_nopause.sv b/Project.sim/sim_2/behav/Project_screentest_nopause.sv new file mode 100644 index 0000000..b2a85e0 --- /dev/null +++ b/Project.sim/sim_2/behav/Project_screentest_nopause.sv @@ -0,0 +1,308 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 4/15/2015 +// +// PLEASE README! +// ============== +// +// This is a self-checking tester for your full MIPS processor +// plus memory-mapped IO. +// +// Use this tester carefully! The names of your top-level input/output +// and internal signals may be different, so modify all of signal names on the +// right-hand-side of the "wire" assigments appearing above the uut +// instantiation. Observe that the uut itself only has clock and reset inputs +// now, and no debug outputs. Also, the parameters specifying the names of the +// memory initialization files must match the actual file names. +// +// If you decide not to use some of these internal signals for debugging, you +// may comment the relevant lines out. Be sure to comment out the +// corresponding "ERROR_*" lines below as well. +// +// Finally, note that in my bitmap memory, each 12-bit color is encoded as +// RRRRGGGGBBBB (i.e., red is most significant). If you have chosen a different +// order for the red/green/blue color values, you may see ERROR signals for the +// colors light up, but there is no error if you are consistent with your +// RGB ordering. +// +////////////////////////////////////////////////////////////////////////////////// + + +module project_screentest; + + // Inputs + reg clk; + reg reset; + + // Signals inside top-level module uut + wire [31:0] pc =uut.pc; // PC + wire [31:0] instr =uut.instr; // instr coming out of instr mem + wire [31:0] mem_addr =uut.mem_addr; // addr sent to data mem + wire mem_wr =uut.mem_wr; // write enable for data mem + wire [31:0] mem_readdata =uut.mem_readdata; // data read from data mem + wire [31:0] mem_writedata =uut.mem_writedata; // write data for data mem + + // Signals inside module uut.mips + wire werf =uut.mips.werf; // WERF = write enable for register file + wire [4:0] alufn =uut.mips.alufn; // ALU function + wire Z =uut.mips.Z; // Zero flag + + // Signals inside module uut.mips.dp (datapath) + wire [31:0] ReadData1 =uut.mips.dp.ReadData1; // Reg[rs] + wire [31:0] ReadData2 =uut.mips.dp.ReadData2; // Reg[rt] + wire [31:0] alu_result =uut.mips.dp.alu_result; // ALU's output + wire [4:0] reg_writeaddr =uut.mips.dp.reg_writeaddr; // destination register + wire [31:0] reg_writedata =uut.mips.dp.reg_writedata; // write data for register file + wire [31:0] signImm =uut.mips.dp.signImm; // sign-/zero-extended immediate + wire [31:0] aluA =uut.mips.dp.aluA; // operand A for ALU + wire [31:0] aluB =uut.mips.dp.aluB; // operand B for ALU + + // Signals inside module uut.mips.c (controller) + wire [1:0] pcsel =uut.mips.c.pcsel; + wire [1:0] wasel =uut.mips.c.wasel; + wire sext =uut.mips.c.sext; + wire bsel =uut.mips.c.bsel; + wire [1:0] wdsel =uut.mips.c.wdsel; + wire wr =uut.mips.c.wr; + wire [1:0] asel =uut.mips.c.asel; + + // Signals related to module memIO (memory + memory-mapped IO) + wire [10:0] smem_addr =uut.smem_addr; // address from vgadisplaydriver to access screen mem + wire [3:0] charcode =uut.charcode; // character code returned by screen mem + wire dmem_wr =uut.io.dmem_wr; + wire smem_wr =uut.io.smem_wr; + + // Signals related to module vgadisplaydriver (display driver) + wire hsync =uut.hsync; + wire vsync =uut.vsync; + wire [3:0] red =uut.red; + wire [3:0] green =uut.green; + wire [3:0] blue =uut.blue; + wire [9:0] x =uut.displaydriver.x; + wire [9:0] y =uut.displaydriver.y; + wire [11:0] bmem_addr =uut.displaydriver.bmem_addr; + wire [11:0] bmem_color =uut.displaydriver.color; + + + // Instantiate the Unit Under Test (UUT) + top uut( + .clk(clk), + .reset(reset) + ); + +// +// CHECK ALL VALUES ABOVE THIS LINE +// YOU SHOULD NOT NEED TO MODIFY ANYTHING BELOW +// + + initial begin + // Initialize Inputs + clk = 0; + reset = 0; + end + + initial begin + #0.5 clk = 0; + forever + #0.5 clk = ~clk; + end + + initial begin + #50 $finish; + end + + + + // SELF-CHECKING CODE + + selfcheck c(); + + wire [31:0] c_pc=c.pc; + wire [31:0] c_instr=c.instr; + wire [31:0] c_mem_addr=c.mem_addr; + wire c_mem_wr=c.mem_wr; + wire [31:0] c_mem_readdata=c.mem_readdata; + wire [31:0] c_mem_writedata=c.mem_writedata; + wire c_werf=c.werf; + wire [4:0] c_alufn=c.alufn; + wire c_Z=c.Z; + wire [31:0] c_ReadData1=c.ReadData1; + wire [31:0] c_ReadData2=c.ReadData2; + wire [31:0] c_alu_result=c.alu_result; + wire [4:0] c_reg_writeaddr=c.reg_writeaddr; + wire [31:0] c_reg_writedata=c.reg_writedata; + wire [31:0] c_signImm=c.signImm; + wire [31:0] c_aluA=c.aluA; + wire [31:0] c_aluB=c.aluB; + wire [1:0] c_pcsel=c.pcsel; + wire [1:0] c_wasel=c.wasel; + wire c_sext=c.sext; + wire c_bsel=c.bsel; + wire [1:0] c_wdsel=c.wdsel; + wire c_wr=c.wr; + wire [1:0] c_asel=c.asel; + wire [10:0] c_smem_addr=c.smem_addr; + wire [3:0] c_charcode=c.charcode; + wire c_dmem_wr=c.dmem_wr; + wire c_smem_wr=c.smem_wr; + wire c_hsync=c.hsync; + wire c_vsync=c.vsync; + wire [3:0] c_red=c.red; + wire [3:0] c_green=c.green; + wire [3:0] c_blue=c.blue; + wire [9:0] c_x=c.x; + wire [9:0] c_y=c.x; + wire [11:0] c_bmem_addr=c.bmem_addr; + wire [11:0] c_bmem_color=c.bmem_color; + + + function mismatch; // some trickery needed to match two values with don't cares + input p, q; // mismatch in a bit position is ignored if q has an 'x' in that bit + integer p, q; + mismatch = (((p ^ q) ^ q) !== q); + endfunction + + wire ERROR = ERROR_pc | ERROR_instr | ERROR_mem_addr | ERROR_mem_wr | ERROR_mem_readdata + | ERROR_mem_writedata | ERROR_werf | ERROR_alufn | ERROR_Z + | ERROR_ReadData1 | ERROR_ReadData2 | ERROR_alu_result | ERROR_reg_writeaddr + | ERROR_reg_writedata | ERROR_signImm | ERROR_aluA | ERROR_aluB + | ERROR_pcsel | ERROR_wasel | ERROR_sext | ERROR_bsel | ERROR_wdsel | ERROR_wr | ERROR_asel + | ERROR_smem_addr | ERROR_charcode | ERROR_dmem_wr | ERROR_smem_wr | ERROR_hsync | ERROR_vsync + | ERROR_red | ERROR_green | ERROR_blue | ERROR_x | ERROR_y | ERROR_bmem_addr | ERROR_bmem_color; + + + wire ERROR_pc = mismatch(pc, c.pc) ? 1'bx : 1'b0; + wire ERROR_instr = mismatch(instr, c.instr) ? 1'bx : 1'b0; + wire ERROR_mem_addr = mismatch(mem_addr, c.mem_addr) ? 1'bx : 1'b0; + wire ERROR_mem_wr = mismatch(mem_wr, c.mem_wr) ? 1'bx : 1'b0; + wire ERROR_mem_readdata = mismatch(mem_readdata, c.mem_readdata) ? 1'bx : 1'b0; + wire ERROR_mem_writedata = c.mem_wr & (mismatch(mem_writedata, c.mem_writedata) ? 1'bx : 1'b0); + wire ERROR_werf = mismatch(werf, c.werf) ? 1'bx : 1'b0; + wire ERROR_alufn = mismatch(alufn, c.alufn) ? 1'bx : 1'b0; + wire ERROR_Z = mismatch(Z, c.Z) ? 1'bx : 1'b0; + wire ERROR_ReadData1 = mismatch(ReadData1, c.ReadData1) ? 1'bx : 1'b0; + wire ERROR_ReadData2 = mismatch(ReadData2, c.ReadData2) ? 1'bx : 1'b0; + wire ERROR_alu_result = mismatch(alu_result, c.alu_result) ? 1'bx : 1'b0; + wire ERROR_reg_writeaddr = c.werf & (mismatch(reg_writeaddr, c.reg_writeaddr) ? 1'bx : 1'b0); + wire ERROR_reg_writedata = c.werf & (mismatch(reg_writedata, c.reg_writedata) ? 1'bx : 1'b0); + wire ERROR_signImm = mismatch(signImm, c.signImm) ? 1'bx : 1'b0; + wire ERROR_aluA = mismatch(aluA, c.aluA) ? 1'bx : 1'b0; + wire ERROR_aluB = mismatch(aluB, c.aluB) ? 1'bx : 1'b0; + wire ERROR_pcsel = mismatch(pcsel, c.pcsel) ? 1'bx : 1'b0; + wire ERROR_wasel = c.werf & (mismatch(wasel, c.wasel) ? 1'bx : 1'b0); + wire ERROR_sext = mismatch(sext, c.sext) ? 1'bx : 1'b0; + wire ERROR_bsel = mismatch(bsel, c.bsel) ? 1'bx : 1'b0; + wire ERROR_wdsel = mismatch(wdsel, c.wdsel) ? 1'bx : 1'b0; + wire ERROR_wr = mismatch(wr, c.wr) ? 1'bx : 1'b0; + wire ERROR_asel = mismatch(asel, c.asel) ? 1'bx : 1'b0; + wire ERROR_smem_addr = mismatch(smem_addr, c.smem_addr) ? 1'bx : 1'b0; + wire ERROR_charcode = mismatch(charcode, c.charcode) ? 1'bx : 1'b0; + wire ERROR_dmem_wr = mismatch(dmem_wr, c.dmem_wr) ? 1'bx : 1'b0; + wire ERROR_smem_wr = mismatch(smem_wr, c.smem_wr) ? 1'bx : 1'b0; + wire ERROR_hsync = mismatch(hsync, c.hsync) ? 1'bx : 1'b0; + wire ERROR_vsync = mismatch(vsync, c.vsync) ? 1'bx : 1'b0; + wire ERROR_red = mismatch(red, c.red) ? 1'bx : 1'b0; + wire ERROR_green = mismatch(green, c.green) ? 1'bx : 1'b0; + wire ERROR_blue = mismatch(blue, c.blue) ? 1'bx : 1'b0; + wire ERROR_x = mismatch(x, c.x) ? 1'bx : 1'b0; + wire ERROR_y = mismatch(y, c.y) ? 1'bx : 1'b0; + wire ERROR_bmem_addr = mismatch(bmem_addr, c.bmem_addr) ? 1'bx : 1'b0; + wire ERROR_bmem_color = mismatch(bmem_color, c.bmem_color) ? 1'bx : 1'b0; + + //initial begin + // $monitor("#%02d {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h%h, 32'h%h, 32'h%h, 1'b%b, 32'h%h, 32'h%h, 1'b%b, 5'b%b, 1'b%b, 32'h%h, 32'h%h, 32'h%h, 5'h%h, 32'h%h, 32'h%h, 32'h%h, 32'h%h, 2'b%b, 2'b%b, 1'b%b, 1'b%b, 2'b%b, 1'b%b, 2'b%b};", + // $time, pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel); + // $monitor("#%02d {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h%h, 4'h%h, 1'b%b, 1'b%b, 1'b%b, 1'b%b, 4'h%h, 4'h%h, 4'h%h, 10'h%h, 10'h%h, 12'h%h, 12'h%h};", + // $time, smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color); + //end + +endmodule + + + +// CHECKER MODULE +module selfcheck(); + reg [31:0] pc; + reg [31:0] instr; + reg [31:0] mem_addr; + reg mem_wr; + reg [31:0] mem_readdata; + reg [31:0] mem_writedata; + reg werf; + reg [4:0] alufn; + reg Z; + reg [31:0] ReadData1; + reg [31:0] ReadData2; + reg [31:0] alu_result; + reg [4:0] reg_writeaddr; + reg [31:0] reg_writedata; + reg [31:0] signImm; + reg [31:0] aluA; + reg [31:0] aluB; + reg [1:0] pcsel; + reg [1:0] wasel; + reg sext; + reg bsel; + reg [1:0] wdsel; + reg wr; + reg [1:0] asel; + reg [10:0] smem_addr; + reg [3:0] charcode; + reg dmem_wr; + reg smem_wr; + reg hsync; + reg vsync; + reg [3:0] red; + reg [3:0] green; + reg [3:0] blue; + reg [9:0] x; + reg [9:0] y; + reg [11:0] bmem_addr; + reg [11:0] bmem_color; + +initial begin +fork + +#00 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000000, 32'h00000020, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'h00, 32'h00000000, 32'h00000020, 32'h00000000, 32'h00000000, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#00 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h000, 10'h000, 12'h000, 12'hf00}; +#01 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000004, 32'h201d203c, 32'h0000203c, 1'b0, 32'hxxxxxxxx, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h0000203c, 5'h1d, 32'h0000203c, 32'h0000203c, 32'h00000000, 32'h0000203c, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#02 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000008, 32'h20040000, 32'h00000000, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b1, 32'h00000000, 32'hxxxxxxxx, 32'h00000000, 5'h04, 32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#03 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000000c, 32'h0c000009, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h00000010, 32'h00000009, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#04 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h23bdfff8, 32'h00002034, 1'b0, 32'hxxxxxxxx, 32'h0000203c, 1'b1, 5'b0xx01, 1'b0, 32'h0000203c, 32'h0000203c, 32'h00002034, 5'h1d, 32'h00002034, 32'hfffffff8, 32'h0000203c, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#04 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#05 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000028, 32'hafbf0004, 32'h00002038, 1'b1, 32'hxxxxxxxx, 32'h00000010, 1'b0, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000010, 32'h00002038, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h00002034, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#05 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b1, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#06 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000002c, 32'hafa40000, 32'h00002034, 1'b1, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000000, 32'h00002034, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00002034, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#07 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000030, 32'h00042400, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'bx0010, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'h04, 32'h00000000, 32'h00002400, 32'h00000010, 32'h00000000, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b01}; +#07 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#08 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h002, 10'h000, 12'h002, 12'hf00}; +#08 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000034, 32'h10800002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000000, 32'h00000000, 2'b01, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#09 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000040, 32'h8fa40000, 32'h00002034, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000000, 32'h00002034, 5'h04, 32'h00000000, 32'h00000000, 32'h00002034, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#10 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000044, 32'h8fbf0004, 32'h00002038, 1'b0, 32'h00000010, 32'h00000010, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000010, 32'h00002038, 5'h1f, 32'h00000010, 32'h00000004, 32'h00002034, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#11 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h23bd0008, 32'h0000203c, 1'b0, 32'hxxxxxxxx, 32'h00002034, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00002034, 32'h0000203c, 5'h1d, 32'h0000203c, 32'h00000008, 32'h00002034, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#12 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000010, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#12 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h003, 10'h000, 12'h003, 12'hf00}; +#13 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000010, 32'h20080002, 32'h00000002, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h00000002, 5'h08, 32'h00000002, 32'h00000002, 32'h00000000, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#14 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'hac084000, 32'h00004000, 1'b1, 32'h00000000, 32'h00000002, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000002, 32'h00004000, 5'hxx, 32'hxxxxxxxx, 32'h00004000, 32'h00000000, 32'h00004000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#14 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b1, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h003, 10'h000, 12'h003, 12'hf00}; +#15 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'h20080003, 32'h00000003, 1'b0, 32'h00000000, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000002, 32'h00000003, 5'h08, 32'h00000003, 32'h00000003, 32'h00000000, 32'h00000003, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#15 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h003, 10'h000, 12'h203, 12'h00f}; +#16 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hac084001, 32'h00004001, 1'b1, 32'h00000001, 32'h00000003, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000003, 32'h00004001, 5'hxx, 32'hxxxxxxxx, 32'h00004001, 32'h00000000, 32'h00004001, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#16 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b1, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h004, 10'h000, 12'h204, 12'h00f}; +#17 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h08000008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#17 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h004, 10'h000, 12'h204, 12'h00f}; +#20 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h005, 10'h000, 12'h205, 12'h00f}; +#24 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h006, 10'h000, 12'h206, 12'h00f}; +#28 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h007, 10'h000, 12'h207, 12'h00f}; +#32 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h008, 10'h000, 12'h208, 12'h00f}; +#36 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h009, 10'h000, 12'h209, 12'h00f}; +#40 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00a, 10'h000, 12'h20a, 12'h00f}; +#44 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00b, 10'h000, 12'h20b, 12'h00f}; +#48 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00c, 10'h000, 12'h20c, 12'h00f}; + +join +end + +endmodule \ No newline at end of file diff --git a/Project.sim/sim_2/behav/bmem_init.txt b/Project.sim/sim_2/behav/bmem_init.txt new file mode 100644 index 0000000..4981092 --- /dev/null +++ b/Project.sim/sim_2/behav/bmem_init.txt @@ -0,0 +1,1024 @@ +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff \ No newline at end of file diff --git a/Project.sim/sim_2/behav/compile.bat b/Project.sim/sim_2/behav/compile.bat new file mode 100644 index 0000000..f662848 --- /dev/null +++ b/Project.sim/sim_2/behav/compile.bat @@ -0,0 +1,10 @@ +@echo off +set xv_path=C:\\Xilinx\\Vivado\\2014.4\\bin +echo "xvlog -m64 -prj project_screentest_vlog.prj" +call %xv_path%/xvlog -m64 -prj project_screentest_vlog.prj -log compile.log +if "%errorlevel%"=="1" goto END +if "%errorlevel%"=="0" goto SUCCESS +:END +exit 1 +:SUCCESS +exit 0 diff --git a/Project.sim/sim_2/behav/compile.log b/Project.sim/sim_2/behav/compile.log new file mode 100644 index 0000000..58a1947 --- /dev/null +++ b/Project.sim/sim_2/behav/compile.log @@ -0,0 +1,57 @@ +Determining compilation order of HDL files. +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/fulladder.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module fulladder +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/adder.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module adder +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/comparator.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module comparator +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/addsub.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module addsub +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/logical.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module logical +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/shifter.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module shifter +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/alu.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module ALU +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/signExtension.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module signExtension +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/xycounter.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module xycounter +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/register_file.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module register_file +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgatimer.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module vgatimer +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/smem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module smem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/controller.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module controller +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/bitmapmem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module bitmapmem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/dmem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module dmem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module datapath +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/debouncer.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module debouncer +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module vgadisplaydriver +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/imem.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module imem +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module memIO +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/mips.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module mips +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module top +INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module project_screentest +WARNING: [VRFC 10-756] identifier ERROR_pc is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv:167] +WARNING: [VRFC 10-756] identifier ERROR_mem_writedata is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv:168] +WARNING: [VRFC 10-756] identifier ERROR_ReadData1 is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv:169] +WARNING: [VRFC 10-756] identifier ERROR_reg_writedata is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv:170] +WARNING: [VRFC 10-756] identifier ERROR_pcsel is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv:171] +WARNING: [VRFC 10-756] identifier ERROR_smem_addr is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv:172] +WARNING: [VRFC 10-756] identifier ERROR_red is used before its declaration [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv:173] +INFO: [VRFC 10-311] analyzing module selfcheck +INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/glbl.v" into library xil_defaultlib +INFO: [VRFC 10-311] analyzing module glbl diff --git a/Project.sim/sim_2/behav/dmem_init.txt b/Project.sim/sim_2/behav/dmem_init.txt new file mode 100644 index 0000000..72cf8de --- /dev/null +++ b/Project.sim/sim_2/behav/dmem_init.txt @@ -0,0 +1 @@ +0 // data memory not used in this program \ No newline at end of file diff --git a/Project.sim/sim_2/behav/elaborate.bat b/Project.sim/sim_2/behav/elaborate.bat new file mode 100644 index 0000000..b8b0057 --- /dev/null +++ b/Project.sim/sim_2/behav/elaborate.bat @@ -0,0 +1,9 @@ +@echo off +set xv_path=C:\\Xilinx\\Vivado\\2014.4\\bin +call %xv_path%/xelab -wto 5f5d7ddd32cb4c0cb289603e426c9fed -m64 --debug typical --relax -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot project_screentest_behav xil_defaultlib.project_screentest xil_defaultlib.glbl -log elaborate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/Project.sim/sim_2/behav/elaborate.log b/Project.sim/sim_2/behav/elaborate.log new file mode 100644 index 0000000..28823fa --- /dev/null +++ b/Project.sim/sim_2/behav/elaborate.log @@ -0,0 +1,39 @@ +Vivado Simulator 2014.4 +Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved. +Running: C:/Xilinx/Vivado/2014.4/bin/unwrapped/win64.o/xelab.exe -wto 5f5d7ddd32cb4c0cb289603e426c9fed --debug typical --relax -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot project_screentest_behav xil_defaultlib.project_screentest xil_defaultlib.glbl -log elaborate.log +Multi-threading is on. Using 2 slave threads. +Starting static elaboration +WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port invert [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/top.v:67] +WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 5 for port WriteAddr [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/datapath.sv:88] +WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 4 for port writedata [C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sources_1/imports/src/memIO.sv:86] +Completed static elaboration +Starting simulation data flow analysis +Completed simulation data flow analysis +Time Resolution for simulation is 1ps +Compiling module xil_defaultlib.imem +Compiling module xil_defaultlib.debouncer +Compiling module xil_defaultlib.controller +Compiling module xil_defaultlib.register_file(Abits=5,Dbits=32,N... +Compiling module xil_defaultlib.signExtension +Compiling module xil_defaultlib.fulladder +Compiling module xil_defaultlib.adder(N=32) +Compiling module xil_defaultlib.addsub(N=32) +Compiling module xil_defaultlib.shifter(N=32) +Compiling module xil_defaultlib.logical(N=32) +Compiling module xil_defaultlib.comparator(N=32) +Compiling module xil_defaultlib.ALU(N=32) +Compiling module xil_defaultlib.datapath +Compiling module xil_defaultlib.mips +Compiling module xil_defaultlib.smem +Compiling module xil_defaultlib.dmem +Compiling module xil_defaultlib.memIO +Compiling module xil_defaultlib.xycounter(width=800,height=525) +Compiling module xil_defaultlib.vgatimer +Compiling module xil_defaultlib.bitmapmem +Compiling module xil_defaultlib.vgadisplaydriver +Compiling module xil_defaultlib.top +Compiling module xil_defaultlib.selfcheck +Compiling module xil_defaultlib.project_screentest +Compiling module xil_defaultlib.glbl +Waiting for 2 sub-compilation(s) to finish... +Built simulation snapshot project_screentest_behav diff --git a/Project.sim/sim_2/behav/glbl.v b/Project.sim/sim_2/behav/glbl.v new file mode 100644 index 0000000..2edbf14 --- /dev/null +++ b/Project.sim/sim_2/behav/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/Project.sim/sim_2/behav/imem_init.txt b/Project.sim/sim_2/behav/imem_init.txt new file mode 100644 index 0000000..0d8b43c --- /dev/null +++ b/Project.sim/sim_2/behav/imem_init.txt @@ -0,0 +1,20 @@ +00000020 +201d203c +20040000 +0c000009 +20080002 +ac084000 +20080003 +ac084001 +08000008 +23bdfff8 +afbf0004 +afa40000 +00042400 +10800002 +2084ffff +1480fffe +8fa40000 +8fbf0004 +23bd0008 +03e00008 \ No newline at end of file diff --git a/Project.sim/sim_2/behav/project_screentest.tcl b/Project.sim/sim_2/behav/project_screentest.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/Project.sim/sim_2/behav/project_screentest.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/Project.sim/sim_2/behav/project_screentest_behav.wdb b/Project.sim/sim_2/behav/project_screentest_behav.wdb new file mode 100644 index 0000000..7427185 Binary files /dev/null and b/Project.sim/sim_2/behav/project_screentest_behav.wdb differ diff --git a/Project.sim/sim_2/behav/project_screentest_vlog.prj b/Project.sim/sim_2/behav/project_screentest_vlog.prj new file mode 100644 index 0000000..2e563c7 --- /dev/null +++ b/Project.sim/sim_2/behav/project_screentest_vlog.prj @@ -0,0 +1,27 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/fulladder.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/adder.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/comparator.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/addsub.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/logical.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/shifter.v" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/alu.v" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/signExtension.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/xycounter.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/register_file.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/vgatimer.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/smem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/controller.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/bitmapmem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/dmem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/datapath.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/debouncer.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/vgadisplaydriver.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/imem.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/memIO.sv" +sv xil_defaultlib "../../../Project.srcs/sources_1/imports/src/mips.sv" +verilog xil_defaultlib "../../../Project.srcs/sources_1/imports/src/top.v" +sv xil_defaultlib "../../../Project.srcs/sim_2/new/Project_screentest_nopause.sv" + +# compile glbl module +verilog xil_defaultlib "glbl.v" diff --git a/Project.sim/sim_2/behav/regd_init.txt b/Project.sim/sim_2/behav/regd_init.txt new file mode 100644 index 0000000..463fdf1 --- /dev/null +++ b/Project.sim/sim_2/behav/regd_init.txt @@ -0,0 +1,32 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 \ No newline at end of file diff --git a/Project.sim/sim_2/behav/simulate.bat b/Project.sim/sim_2/behav/simulate.bat new file mode 100644 index 0000000..392cafc --- /dev/null +++ b/Project.sim/sim_2/behav/simulate.bat @@ -0,0 +1,9 @@ +@echo off +set xv_path=C:\\Xilinx\\Vivado\\2014.4\\bin +call %xv_path%/xsim project_screentest_behav -key {Behavioral:sim_2:Functional:project_screentest} -tclbatch project_screentest.tcl -log simulate.log +if "%errorlevel%"=="0" goto SUCCESS +if "%errorlevel%"=="1" goto END +:END +exit 1 +:SUCCESS +exit 0 diff --git a/Project.sim/sim_2/behav/simulate.log b/Project.sim/sim_2/behav/simulate.log new file mode 100644 index 0000000..7a9b9d9 --- /dev/null +++ b/Project.sim/sim_2/behav/simulate.log @@ -0,0 +1,3 @@ +Vivado Simulator 2014.4 +Time resolution is 1 ps +$finish called at time : 50 ns : File "C:/Users/jrpotter/Documents/Vivado/Project/Project.srcs/sim_2/new/Project_screentest_nopause.sv" Line 113 diff --git a/Project.sim/sim_2/behav/smem_init.txt b/Project.sim/sim_2/behav/smem_init.txt new file mode 100644 index 0000000..7f4ac33 --- /dev/null +++ b/Project.sim/sim_2/behav/smem_init.txt @@ -0,0 +1,1200 @@ +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 +0 +1 \ No newline at end of file diff --git a/Project.sim/sim_2/behav/webtalk.jou b/Project.sim/sim_2/behav/webtalk.jou new file mode 100644 index 0000000..c3f7de6 --- /dev/null +++ b/Project.sim/sim_2/behav/webtalk.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Webtalk v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Thu Apr 16 13:13:02 2015 +# Process ID: 6464 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/webtalk.log +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav\webtalk.jou +#----------------------------------------------------------- +source C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Project.sim/sim_2/behav/webtalk.log b/Project.sim/sim_2/behav/webtalk.log new file mode 100644 index 0000000..a8c1227 --- /dev/null +++ b/Project.sim/sim_2/behav/webtalk.log @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Thu Apr 16 13:13:02 2015 +# Process ID: 6464 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/webtalk.log +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav\webtalk.jou +#----------------------------------------------------------- +source C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-186] 'C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Apr 16 13:13:06 2015. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2014.4/doc/webtalk_introduction.html. +INFO: [Common 17-206] Exiting Webtalk at Thu Apr 16 13:13:06 2015... diff --git a/Project.sim/sim_2/behav/webtalk_6464.backup.jou b/Project.sim/sim_2/behav/webtalk_6464.backup.jou new file mode 100644 index 0000000..cabb86c --- /dev/null +++ b/Project.sim/sim_2/behav/webtalk_6464.backup.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# Webtalk v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Thu Apr 16 11:40:38 2015 +# Process ID: 2400 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/webtalk.log +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav\webtalk.jou +#----------------------------------------------------------- +source C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/Project.sim/sim_2/behav/webtalk_6464.backup.log b/Project.sim/sim_2/behav/webtalk_6464.backup.log new file mode 100644 index 0000000..caa34f8 --- /dev/null +++ b/Project.sim/sim_2/behav/webtalk_6464.backup.log @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2014.4 (64-bit) +# SW Build 1071353 on Tue Nov 18 18:24:04 MST 2014 +# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 +# Start of session at: Thu Apr 16 11:40:38 2015 +# Process ID: 2400 +# Log file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/webtalk.log +# Journal file: C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav\webtalk.jou +#----------------------------------------------------------- +source C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/xsim_webtalk.tcl -notrace +INFO: [Common 17-186] 'C:/Users/jrpotter/Documents/Vivado/Project/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Apr 16 11:40:41 2015. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2014.4/doc/webtalk_introduction.html. +INFO: [Common 17-206] Exiting Webtalk at Thu Apr 16 11:40:41 2015... diff --git a/Project.sim/sim_2/behav/xelab.pb b/Project.sim/sim_2/behav/xelab.pb new file mode 100644 index 0000000..b8cc60e Binary files /dev/null and b/Project.sim/sim_2/behav/xelab.pb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/Compile_Options.txt b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/Compile_Options.txt new file mode 100644 index 0000000..1a1955c --- /dev/null +++ b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "5f5d7ddd32cb4c0cb289603e426c9fed" --debug "typical" --relax -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "project_screentest_behav" "xil_defaultlib.project_screentest" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/.xsim_webtallk.info b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/.xsim_webtallk.info new file mode 100644 index 0000000..4877be1 --- /dev/null +++ b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/.xsim_webtallk.info @@ -0,0 +1,5 @@ +1429198835 +1429204377 +3 +1 +5f5d7ddd32cb4c0cb289603e426c9fed diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.html b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.html new file mode 100644 index 0000000..20e9414 --- /dev/null +++ b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.html @@ -0,0 +1,54 @@ +Device Usage Statistics Report +

XSIM Usage Report


+ + + + + + + + + + + + + + + + + +
software_version_and_target_device
date_generatedThu Apr 16 13:12:57 2015product_versionXSIM v2014.4 (64-bit)
build_version1071353os_platformWIN64
registration_id210990371_0_0_454tool_flowxsim_vivado
betaFALSEroute_designFALSE
target_familynot_applicabletarget_devicenot_applicable
target_packagenot_applicabletarget_speednot_applicable
random_idcbe99d29-70fc-410f-b2e1-f5330b3232ceproject_id5f5d7ddd32cb4c0cb289603e426c9fed
project_iteration2

+ + + + + + + + +
user_environment
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
cpu_nameIntel(R) Core(TM) i5-3320M CPU @ 2.60GHzcpu_speed2594 MHz
total_processors1system_ram3.000 GB

+ + +
vivado_usage

+ + + + +
xsim
+ + + + +
command_line_options
command=xsimrunall=false
+
+ + + + + + + +
usage
trace_waveform=trueruntime=50 nsiteration=0simulation_time=0.23_sec
simulation_memory=18080_KB
+

+ + diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.xml b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..8a36f27 --- /dev/null +++ b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,45 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ + +
+
+ + + + + +
+
+
+ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.dbg b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.dbg new file mode 100644 index 0000000..13458c3 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.dbg differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.mem b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.mem new file mode 100644 index 0000000..d9df0da Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.mem differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.reloc b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.reloc new file mode 100644 index 0000000..e514512 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.reloc differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.rtti b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.rtti new file mode 100644 index 0000000..c22fa37 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.rtti differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.svtype b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.svtype new file mode 100644 index 0000000..5142c79 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.svtype differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.type b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.type new file mode 100644 index 0000000..14a09a2 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.type differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.xdbg b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.xdbg new file mode 100644 index 0000000..d67c08d Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsim.xdbg differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimcrash.log b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimk.exe b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimk.exe new file mode 100644 index 0000000..ae32d24 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimk.exe differ diff --git a/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimkernel.log b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimkernel.log new file mode 100644 index 0000000..4fde30d --- /dev/null +++ b/Project.sim/sim_2/behav/xsim.dir/project_screentest_behav/xsimkernel.log @@ -0,0 +1,7 @@ +Running: xsim.dir/project_screentest_behav/xsimk.exe -simmode gui -wdb project_screentest_behav.wdb -simrunnum 0 -socket 62791 +Design successfully loaded +Design Loading Memory Usage: 17456 KB (Peak: 17456 KB) +Design Loading CPU Usage: 218 ms +Simulation completed +Simulation Memory Usage: 18080 KB (Peak: 18080 KB) +Simulation CPU Usage: 234 ms diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/@a@l@u.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/@a@l@u.sdb new file mode 100644 index 0000000..7fbc2e0 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/@a@l@u.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/adder.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/adder.sdb new file mode 100644 index 0000000..903b1e7 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/adder.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/addsub.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/addsub.sdb new file mode 100644 index 0000000..fbc6f4b Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/addsub.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/bitmapmem.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/bitmapmem.sdb new file mode 100644 index 0000000..e10b34a Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/bitmapmem.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/comparator.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/comparator.sdb new file mode 100644 index 0000000..8e24032 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/comparator.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/controller.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/controller.sdb new file mode 100644 index 0000000..f379756 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/controller.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/datapath.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/datapath.sdb new file mode 100644 index 0000000..a511eb2 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/datapath.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/debouncer.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/debouncer.sdb new file mode 100644 index 0000000..972b19d Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/debouncer.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/dmem.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/dmem.sdb new file mode 100644 index 0000000..7815431 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/dmem.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/fulladder.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/fulladder.sdb new file mode 100644 index 0000000..c01450a Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/fulladder.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/glbl.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/glbl.sdb new file mode 100644 index 0000000..3741efe Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/glbl.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/imem.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/imem.sdb new file mode 100644 index 0000000..8bed196 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/imem.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/logical.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/logical.sdb new file mode 100644 index 0000000..d35d77e Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/logical.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/mem@i@o.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/mem@i@o.sdb new file mode 100644 index 0000000..0119c04 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/mem@i@o.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/mips.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/mips.sdb new file mode 100644 index 0000000..68b1501 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/mips.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/project_screentest.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/project_screentest.sdb new file mode 100644 index 0000000..48494c9 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/project_screentest.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/register_file.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/register_file.sdb new file mode 100644 index 0000000..ede8a8a Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/register_file.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/selfcheck.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/selfcheck.sdb new file mode 100644 index 0000000..c337610 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/selfcheck.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/shifter.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/shifter.sdb new file mode 100644 index 0000000..5dd691e Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/shifter.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/sign@extension.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/sign@extension.sdb new file mode 100644 index 0000000..1744672 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/sign@extension.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/smem.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/smem.sdb new file mode 100644 index 0000000..7f2e173 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/smem.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/top.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/top.sdb new file mode 100644 index 0000000..bc4f41f Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/top.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/vgadisplaydriver.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/vgadisplaydriver.sdb new file mode 100644 index 0000000..3c997ad Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/vgadisplaydriver.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/vgatimer.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/vgatimer.sdb new file mode 100644 index 0000000..da9c4b6 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/vgatimer.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/xycounter.sdb b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/xycounter.sdb new file mode 100644 index 0000000..b6f9c8a Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xil_defaultlib/xycounter.sdb differ diff --git a/Project.sim/sim_2/behav/xsim.dir/xsim.svtype b/Project.sim/sim_2/behav/xsim.dir/xsim.svtype new file mode 100644 index 0000000..5142c79 Binary files /dev/null and b/Project.sim/sim_2/behav/xsim.dir/xsim.svtype differ diff --git a/Project.sim/sim_2/behav/xvlog.pb b/Project.sim/sim_2/behav/xvlog.pb new file mode 100644 index 0000000..d4da740 Binary files /dev/null and b/Project.sim/sim_2/behav/xvlog.pb differ diff --git a/Project.srcs/constrs_1/imports/src/master.xdc b/Project.srcs/constrs_1/imports/src/master.xdc new file mode 100644 index 0000000..04b6c61 --- /dev/null +++ b/Project.srcs/constrs_1/imports/src/master.xdc @@ -0,0 +1,721 @@ +## This file is a general .xdc for the Nexys4 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +## Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ +set_property PACKAGE_PIN E3 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + +## Switches +## Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 +#set_property PACKAGE_PIN U9 [get_ports {sw[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +## Bank = 34, Pin name = IO_25_34, Sch name = SW1 +#set_property PACKAGE_PIN U8 [get_ports {sw[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +## Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 +#set_property PACKAGE_PIN R7 [get_ports {sw[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +## Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 +#set_property PACKAGE_PIN R6 [get_ports {sw[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +## Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 +#set_property PACKAGE_PIN R5 [get_ports {sw[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +## Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 +#set_property PACKAGE_PIN V7 [get_ports {sw[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +## Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 +#set_property PACKAGE_PIN V6 [get_ports {sw[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +## Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 +#set_property PACKAGE_PIN V5 [get_ports {sw[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +## Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 +#set_property PACKAGE_PIN U4 [get_ports {sw[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +## Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 +#set_property PACKAGE_PIN V2 [get_ports {sw[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +## Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 +#set_property PACKAGE_PIN U2 [get_ports {sw[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +## Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 +#set_property PACKAGE_PIN T3 [get_ports {sw[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +## Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 +#set_property PACKAGE_PIN T1 [get_ports {sw[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +## Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 +#set_property PACKAGE_PIN R3 [get_ports {sw[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +## Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 +#set_property PACKAGE_PIN P3 [get_ports {sw[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +## Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 +#set_property PACKAGE_PIN P4 [get_ports {sw[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + + +## LEDs +## Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 +#set_property PACKAGE_PIN T8 [get_ports {led[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +## Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 +#set_property PACKAGE_PIN V9 [get_ports {led[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +## Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 +#set_property PACKAGE_PIN R8 [get_ports {led[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +## Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 +#set_property PACKAGE_PIN T6 [get_ports {led[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +## Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 +#set_property PACKAGE_PIN T5 [get_ports {led[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +## Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 +#set_property PACKAGE_PIN T4 [get_ports {led[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +## Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 +#set_property PACKAGE_PIN U7 [get_ports {led[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +## Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 +#set_property PACKAGE_PIN U6 [get_ports {led[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +## Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 +#set_property PACKAGE_PIN V4 [get_ports {led[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] +## Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 +#set_property PACKAGE_PIN U3 [get_ports {led[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] +## Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 +#set_property PACKAGE_PIN V1 [get_ports {led[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] +## Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 +#set_property PACKAGE_PIN R1 [get_ports {led[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] +## Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 +#set_property PACKAGE_PIN P5 [get_ports {led[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] +## Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 +#set_property PACKAGE_PIN U1 [get_ports {led[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] +## Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 +#set_property PACKAGE_PIN R2 [get_ports {led[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] +## Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 +#set_property PACKAGE_PIN P2 [get_ports {led[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] + +## Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R +#set_property PACKAGE_PIN K5 [get_ports RGB1_Red] + #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Red] +## Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G +#set_property PACKAGE_PIN F13 [get_ports RGB1_Green] + #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Green] +## Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B +#set_property PACKAGE_PIN F6 [get_ports RGB1_Blue] + #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Blue] +## Bank = 34, Pin name = IO_0_34, Sch name = LED17_R +#set_property PACKAGE_PIN K6 [get_ports RGB2_Red] + #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Red] +## Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G +#set_property PACKAGE_PIN H6 [get_ports RGB2_Green] + #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Green] +## Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B +#set_property PACKAGE_PIN L16 [get_ports RGB2_Blue] + #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Blue] + + + +##7 segment display +## Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA +set_property PACKAGE_PIN L3 [get_ports {segments[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {segments[7]}] +## Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB +set_property PACKAGE_PIN N1 [get_ports {segments[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {segments[6]}] +## Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC +set_property PACKAGE_PIN L5 [get_ports {segments[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {segments[5]}] +## Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD +set_property PACKAGE_PIN L4 [get_ports {segments[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {segments[4]}] +## Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE +set_property PACKAGE_PIN K3 [get_ports {segments[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {segments[3]}] +## Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF +set_property PACKAGE_PIN M2 [get_ports {segments[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {segments[2]}] +## Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG +set_property PACKAGE_PIN L6 [get_ports {segments[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {segments[1]}] +## Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP +set_property PACKAGE_PIN M4 [get_ports segments[0]] + set_property IOSTANDARD LVCMOS33 [get_ports segments[0]] + +## Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 +set_property PACKAGE_PIN N6 [get_ports {digitselect[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[0]}] +## Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 +set_property PACKAGE_PIN M6 [get_ports {digitselect[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[1]}] +## Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 +set_property PACKAGE_PIN M3 [get_ports {digitselect[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[2]}] +## Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 +set_property PACKAGE_PIN N5 [get_ports {digitselect[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[3]}] +## Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 +set_property PACKAGE_PIN N2 [get_ports {digitselect[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[4]}] +## Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 +set_property PACKAGE_PIN N4 [get_ports {digitselect[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[5]}] +## Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 +set_property PACKAGE_PIN L1 [get_ports {digitselect[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[6]}] +## Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 +set_property PACKAGE_PIN M1 [get_ports {digitselect[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {digitselect[7]}] + + + +##Buttons +## Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET +set_property PACKAGE_PIN C12 [get_ports reset] + set_property IOSTANDARD LVCMOS33 [get_ports reset] +## Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC +#set_property PACKAGE_PIN E16 [get_ports btnC] + #set_property IOSTANDARD LVCMOS33 [get_ports btnC] +## Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU +#set_property PACKAGE_PIN F15 [get_ports btnU] + #set_property IOSTANDARD LVCMOS33 [get_ports btnU] +## Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL +#set_property PACKAGE_PIN T16 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +## Bank = 14, Pin name = IO_25_14, Sch name = BTNR +#set_property PACKAGE_PIN R10 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +## Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND +#set_property PACKAGE_PIN V10 [get_ports btnD] + #set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +## Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 +#set_property PACKAGE_PIN B13 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +## Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 +#set_property PACKAGE_PIN F14 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +## Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 +#set_property PACKAGE_PIN D17 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +## Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 +#set_property PACKAGE_PIN E17 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +## Bank = 15, Pin name = IO_0_15, Sch name = JA7 +#set_property PACKAGE_PIN G13 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +## Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8 +#set_property PACKAGE_PIN C17 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +## Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9 +#set_property PACKAGE_PIN D18 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +## Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10 +#set_property PACKAGE_PIN E18 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +## Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 +#set_property PACKAGE_PIN G14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +## Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 +#set_property PACKAGE_PIN P15 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +## Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3 +#set_property PACKAGE_PIN V11 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +## Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4 +#set_property PACKAGE_PIN V15 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +## Bank = 15, Pin name = IO_25_15, Sch name = JB7 +#set_property PACKAGE_PIN K16 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +## Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8 +#set_property PACKAGE_PIN R16 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +## Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9 +#set_property PACKAGE_PIN T9 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +## Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 +#set_property PACKAGE_PIN U11 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +## Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 +#set_property PACKAGE_PIN K2 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +## Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 +#set_property PACKAGE_PIN E7 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +## Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 +#set_property PACKAGE_PIN J3 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +## Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 +#set_property PACKAGE_PIN J4 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +## Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 +#set_property PACKAGE_PIN K1 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +## Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 +#set_property PACKAGE_PIN E6 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +## Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 +#set_property PACKAGE_PIN J2 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +## Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 +#set_property PACKAGE_PIN G6 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + + +##Pmod Header JD +## Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1 +#set_property PACKAGE_PIN H4 [get_ports {JD[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}] +## Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2 +#set_property PACKAGE_PIN H1 [get_ports {JD[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}] +## Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3 +#set_property PACKAGE_PIN G1 [get_ports {JD[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}] +## Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4 +#set_property PACKAGE_PIN G3 [get_ports {JD[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}] +## Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7 +#set_property PACKAGE_PIN H2 [get_ports {JD[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}] +## Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8 +#set_property PACKAGE_PIN G4 [get_ports {JD[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}] +## Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9 +#set_property PACKAGE_PIN G2 [get_ports {JD[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}] +## Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10 +#set_property PACKAGE_PIN F3 [get_ports {JD[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}] + + + +##Pmod Header JXADC +## Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P +#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +## Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P +#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +## Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P +#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +## Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P +#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +## Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N +#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +## Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N +#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +## Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N +#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +## Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N +#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +## Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0 +set_property PACKAGE_PIN A3 [get_ports {red[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {red[0]}] +## Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1 +set_property PACKAGE_PIN B4 [get_ports {red[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {red[1]}] +## Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2 +set_property PACKAGE_PIN C5 [get_ports {red[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {red[2]}] +## Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3 +set_property PACKAGE_PIN A4 [get_ports {red[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {red[3]}] +## Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0 +set_property PACKAGE_PIN B7 [get_ports {blue[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {blue[0]}] +## Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1 +set_property PACKAGE_PIN C7 [get_ports {blue[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {blue[1]}] +## Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2 +set_property PACKAGE_PIN D7 [get_ports {blue[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {blue[2]}] +## Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3 +set_property PACKAGE_PIN D8 [get_ports {blue[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {blue[3]}] +## Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0 +set_property PACKAGE_PIN C6 [get_ports {green[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {green[0]}] +## Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1 +set_property PACKAGE_PIN A5 [get_ports {green[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {green[1]}] +## Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2 +set_property PACKAGE_PIN B6 [get_ports {green[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {green[2]}] +## Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3 +set_property PACKAGE_PIN A6 [get_ports {green[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {green[3]}] +## Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS +set_property PACKAGE_PIN B11 [get_ports hsync] + set_property IOSTANDARD LVCMOS33 [get_ports hsync] +## Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS +set_property PACKAGE_PIN B12 [get_ports vsync] + set_property IOSTANDARD LVCMOS33 [get_ports vsync] + + + +##Micro SD Connector +## Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET +#set_property PACKAGE_PIN E2 [get_ports sdReset] + #set_property IOSTANDARD LVCMOS33 [get_ports sdReset] +## Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD +#set_property PACKAGE_PIN A1 [get_ports sdCD] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCD] +## Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK +#set_property PACKAGE_PIN B1 [get_ports sdSCK] + #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK] +## Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD +#set_property PACKAGE_PIN C1 [get_ports sdCmd] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd] +## Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0 +#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}] +## Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1 +#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}] +## Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2 +#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}] +## Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3 +#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}] + + + +##Accelerometer +## Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO +#set_property PACKAGE_PIN D13 [get_ports aclMISO] + #set_property IOSTANDARD LVCMOS33 [get_ports aclMISO] +## Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI +#set_property PACKAGE_PIN B14 [get_ports aclMOSI] + #set_property IOSTANDARD LVCMOS33 [get_ports aclMOSI] +## Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK +#set_property PACKAGE_PIN D15 [get_ports aclSCK] + #set_property IOSTANDARD LVCMOS33 [get_ports aclSCK] +## Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN +#set_property PACKAGE_PIN C15 [get_ports aclSS] + #set_property IOSTANDARD LVCMOS33 [get_ports aclSS] +## Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1 +#set_property PACKAGE_PIN C16 [get_ports aclInt1] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1] +## Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2 +#set_property PACKAGE_PIN E15 [get_ports aclInt2] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2] + + + +##Temperature Sensor +## Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL +#set_property PACKAGE_PIN F16 [get_ports tmpSCL] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL] +## Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA +#set_property PACKAGE_PIN G16 [get_ports tmpSDA] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA] +## Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT +#set_property PACKAGE_PIN D14 [get_ports tmpInt] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt] +## Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT +#set_property PACKAGE_PIN C14 [get_ports tmpCT] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT] + + + +##Omnidirectional Microphone +## Bank = 35, Pin name = IO_25_35, Sch name = M_CLK +#set_property PACKAGE_PIN J5 [get_ports micClk] + #set_property IOSTANDARD LVCMOS33 [get_ports micClk] +## Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA +#set_property PACKAGE_PIN H5 [get_ports micData] + #set_property IOSTANDARD LVCMOS33 [get_ports micData] +## Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL +#set_property PACKAGE_PIN F5 [get_ports micLRSel] + #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel] + + + +##PWM Audio Amplifier +## Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM +#set_property PACKAGE_PIN A11 [get_ports ampPWM] + #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM] +## Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD +#set_property PACKAGE_PIN D12 [get_ports ampSD] + #set_property IOSTANDARD LVCMOS33 [get_ports ampSD] + + +##USB-RS232 Interface +## Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN +#set_property PACKAGE_PIN C4 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +## Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT +#set_property PACKAGE_PIN D4 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] +## Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS +#set_property PACKAGE_PIN D3 [get_ports RsCts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsCts] +## Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS +#set_property PACKAGE_PIN E5 [get_ports RsRts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRts] + + + +##USB HID (PS/2) +## Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK +set_property PACKAGE_PIN F4 [get_ports ps2_clk] + set_property IOSTANDARD LVCMOS33 [get_ports ps2_clk] + set_property PULLUP true [get_ports ps2_clk] +## Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA +set_property PACKAGE_PIN B2 [get_ports ps2_data] + set_property IOSTANDARD LVCMOS33 [get_ports ps2_data] + set_property PULLUP true [get_ports ps2_data] + + + +##SMSC Ethernet PHY +## Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC +#set_property PACKAGE_PIN C9 [get_ports PhyMdc] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc] +## Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO +#set_property PACKAGE_PIN A9 [get_ports PhyMdio] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio] +## Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN +#set_property PACKAGE_PIN B3 [get_ports PhyRstn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn] +## Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV +#set_property PACKAGE_PIN D9 [get_ports PhyCrs] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs] +## Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR +#set_property PACKAGE_PIN C10 [get_ports PhyRxErr] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr] +## Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0 +#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}] +## Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1 +#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}] +## Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN +#set_property PACKAGE_PIN B9 [get_ports PhyTxEn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn] +## Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0 +#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}] +## Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1 +#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}] +## Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK +#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz] +## Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN +#set_property PACKAGE_PIN B8 [get_ports PhyIntn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn] + + + +##Quad SPI Flash +## Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK +#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}] +## Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0 +#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +## Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1 +#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +## Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2 +#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +## Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3 +#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +## Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN +#set_property PACKAGE_PIN L13 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + + + +##Cellular RAM +## Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK +#set_property PACKAGE_PIN T15 [get_ports RamCLK] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCLK] +## Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN +#set_property PACKAGE_PIN T13 [get_ports RamADVn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamADVn] +## Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN +#set_property PACKAGE_PIN L18 [get_ports RamCEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCEn] +## Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE +#set_property PACKAGE_PIN J14 [get_ports RamCRE] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCRE] +## Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN +#set_property PACKAGE_PIN H14 [get_ports RamOEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamOEn] +## Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN +#set_property PACKAGE_PIN R11 [get_ports RamWEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWEn] +## Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN +#set_property PACKAGE_PIN J15 [get_ports RamLBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamLBn] +## Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN +#set_property PACKAGE_PIN J13 [get_ports RamUBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamUBn] +## Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT +#set_property PACKAGE_PIN T14 [get_ports RamWait] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWait] + +## Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0 +#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}] +## Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1 +#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}] +## Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2 +#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}] +## Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3 +#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}] +## Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4 +#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}] +## Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5 +#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}] +## Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6 +#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}] +## Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7 +#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}] +## Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8 +#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}] +## Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9 +#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}] +## Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10 +#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}] +## Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11 +#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}] +## Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12 +#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}] +## Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13 +#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}] +## Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14 +#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}] +## Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15 +#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}] + +## Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0 +#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}] +## Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1 +#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}] +## Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2 +#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}] +## Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3 +#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}] +## Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4 +#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}] +## Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5 +#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}] +## Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6 +#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}] +## Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7 +#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}] +## Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8 +#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}] +## Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9 +#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}] +## Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10 +#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}] +## Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11 +#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}] +## Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12 +#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}] +## Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13 +#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}] +## Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14 +#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}] +## Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15 +#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}] +## Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16 +#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}] +## Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17 +#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}] +## Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18 +#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}] +## Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19 +#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}] +## Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20 +#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}] +## Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21 +#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}] +## Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22 +#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}] + \ No newline at end of file diff --git a/Project.srcs/sim_1/imports/src/Lab10_test_sqr.sv b/Project.srcs/sim_1/imports/src/Lab10_test_sqr.sv new file mode 100644 index 0000000..94fa3ac --- /dev/null +++ b/Project.srcs/sim_1/imports/src/Lab10_test_sqr.sv @@ -0,0 +1,246 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 3/26/2015 +// +// This is a self-checking tester for your full MIPS processor +// (Lab 10 and Project). Use the 2nd test program provided under Lab 10, +// i.e., initialize instruction memory with test2.txt, and data memory +// with test2_data.txt. +// +// Use this tester carefully! The names of your top-level input/output +// and internal signals may be different, so modify all of signal names on the +// right-hand-side of the "wire" assigments appearing above the uut +// instantiation. Observe that the uut itself only has clock and reset inputs +// now, and no debug outputs. Instead, the internal signals are "pulled out" +// using the member selection, or dot, operator ("."). +// +// If you decide not to use some of these internal signals for debugging, you +// may comment the relevant lines out. Be sure to comment out the +// corresponding "ERROR_*" lines below as well. +// +////////////////////////////////////////////////////////////////////////////////// + + +module mips_test_sqr; + + // Inputs + reg clk; + reg reset; + + // Signals inside top-level module uut + wire [31:0] pc =uut.pc; // PC + wire [31:0] instr =uut.instr; // instr coming out of instr mem + wire [31:0] mem_addr =uut.mem_addr; // addr sent to data mem + wire mem_wr =uut.mem_wr; // write enable for data mem + wire [31:0] mem_readdata =uut.mem_readdata; // data read from data mem + wire [31:0] mem_writedata =uut.mem_writedata; // write data for data mem + + // Signals inside module uut.mips + wire werf =uut.mips.werf; // WERF = write enable for register file + wire [4:0] alufn =uut.mips.alufn; // ALU function + wire Z =uut.mips.Z; // Zero flag + + // Signals inside module uut.mips.dp (datapath) + wire [31:0] ReadData1 =uut.mips.dp.ReadData1; // Reg[rs] + wire [31:0] ReadData2 =uut.mips.dp.ReadData2; // Reg[rt] + wire [31:0] alu_result =uut.mips.dp.alu_result; // ALU's output + wire [4:0] reg_writeaddr =uut.mips.dp.reg_writeaddr; // destination register + wire [31:0] reg_writedata =uut.mips.dp.reg_writedata; // write data for register file + wire [31:0] signImm =uut.mips.dp.signImm; // sign-/zero-extended immediate + wire [31:0] aluA =uut.mips.dp.aluA; // operand A for ALU + wire [31:0] aluB =uut.mips.dp.aluB; // operand B for ALU + + // Signals inside module uut.mips.c (controller) + wire [1:0] pcsel =uut.mips.c.pcsel; + wire [1:0] wasel =uut.mips.c.wasel; + wire sext =uut.mips.c.sext; + wire bsel =uut.mips.c.bsel; + wire [1:0] wdsel =uut.mips.c.wdsel; + wire wr =uut.mips.c.wr; + wire [1:0] asel =uut.mips.c.asel; + + // Display Wires + wire hsync, vsync; + wire [3:0] red, green, blue; + + // Instantiate the Unit Under Test (UUT) + top uut( + .clk(clk), .reset(reset), + .hsync(hsync), .vsync(vsync), + .red(red), .green(green), .blue(blue) + ); + + initial begin + // Initialize Inputs + clk = 0; + reset = 1; + end + + initial begin + #0.5 clk = 0; + forever + #0.5 clk = ~clk; + end + + initial begin + #50 $finish; + end + + + + // SELF-CHECKING CODE + + /*selfcheck c(); + + wire [31:0] c_pc=c.pc; + wire [31:0] c_instr=c.instr; + wire [31:0] c_mem_addr=c.mem_addr; + wire c_mem_wr=c.mem_wr; + wire [31:0] c_mem_readdata=c.mem_readdata; + wire [31:0] c_mem_writedata=c.mem_writedata; + wire c_werf=c.werf; + wire [4:0] c_alufn=c.alufn; + wire c_Z=c.Z; + wire [31:0] c_ReadData1=c.ReadData1; + wire [31:0] c_ReadData2=c.ReadData2; + wire [31:0] c_alu_result=c.alu_result; + wire [4:0] c_reg_writeaddr=c.reg_writeaddr; + wire [31:0] c_reg_writedata=c.reg_writedata; + wire [31:0] c_signImm=c.signImm; + wire [31:0] c_aluA=c.aluA; + wire [31:0] c_aluB=c.aluB; + wire [1:0] c_pcsel=c.pcsel; + wire [1:0] c_wasel=c.wasel; + wire c_sext=c.sext; + wire c_bsel=c.bsel; + wire [1:0] c_wdsel=c.wdsel; + wire c_wr=c.wr; + wire [1:0] c_asel=c.asel; + + + function mismatch; // some trickery needed to match two values with don't cares + input p, q; // mismatch in a bit position is ignored if q has an 'x' in that bit + integer p, q; + mismatch = (((p ^ q) ^ q) !== q); + endfunction + + wire ERROR = ERROR_pc | ERROR_instr | ERROR_mem_addr | ERROR_mem_wr | ERROR_mem_readdata + | ERROR_mem_writedata | ERROR_werf | ERROR_alufn | ERROR_Z + | ERROR_ReadData1 | ERROR_ReadData2 | ERROR_alu_result | ERROR_reg_writeaddr + | ERROR_reg_writedata | ERROR_signImm | ERROR_aluA | ERROR_aluB + | ERROR_pcsel | ERROR_wasel | ERROR_sext | ERROR_bsel | ERROR_wdsel | ERROR_wr | ERROR_asel; + + + wire ERROR_pc = mismatch(pc, c.pc) ? 1'bx : 1'b0; + wire ERROR_instr = mismatch(instr, c.instr) ? 1'bx : 1'b0; + wire ERROR_mem_addr = mismatch(mem_addr, c.mem_addr) ? 1'bx : 1'b0; + wire ERROR_mem_wr = mismatch(mem_wr, c.mem_wr) ? 1'bx : 1'b0; + wire ERROR_mem_readdata = mismatch(mem_readdata, c.mem_readdata) ? 1'bx : 1'b0; + wire ERROR_mem_writedata = c.mem_wr & (mismatch(mem_writedata, c.mem_writedata) ? 1'bx : 1'b0); + wire ERROR_werf = mismatch(werf, c.werf) ? 1'bx : 1'b0; + wire ERROR_alufn = mismatch(alufn, c.alufn) ? 1'bx : 1'b0; + wire ERROR_Z = mismatch(Z, c.Z) ? 1'bx : 1'b0; + wire ERROR_ReadData1 = mismatch(ReadData1, c.ReadData1) ? 1'bx : 1'b0; + wire ERROR_ReadData2 = mismatch(ReadData2, c.ReadData2) ? 1'bx : 1'b0; + wire ERROR_alu_result = mismatch(alu_result, c.alu_result) ? 1'bx : 1'b0; + wire ERROR_reg_writeaddr = c.werf & (mismatch(reg_writeaddr, c.reg_writeaddr) ? 1'bx : 1'b0); + wire ERROR_reg_writedata = c.werf & (mismatch(reg_writedata, c.reg_writedata) ? 1'bx : 1'b0); + wire ERROR_signImm = mismatch(signImm, c.signImm) ? 1'bx : 1'b0; + wire ERROR_aluA = mismatch(aluA, c.aluA) ? 1'bx : 1'b0; + wire ERROR_aluB = mismatch(aluB, c.aluB) ? 1'bx : 1'b0; + wire ERROR_pcsel = mismatch(pcsel, c.pcsel) ? 1'bx : 1'b0; + wire ERROR_wasel = c.werf & (mismatch(wasel, c.wasel) ? 1'bx : 1'b0); + wire ERROR_sext = mismatch(sext, c.sext) ? 1'bx : 1'b0; + wire ERROR_bsel = mismatch(bsel, c.bsel) ? 1'bx : 1'b0; + wire ERROR_wdsel = mismatch(wdsel, c.wdsel) ? 1'bx : 1'b0; + wire ERROR_wr = mismatch(wr, c.wr) ? 1'bx : 1'b0; + wire ERROR_asel = mismatch(asel, c.asel) ? 1'bx : 1'b0; + + + initial begin + $monitor("#%02d {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h%h, 32'h%h, 32'h%h, 1'b%b, 32'h%h, 32'h%h, 1'b%b, 5'b%b, 1'b%b, 32'h%h, 32'h%h, 32'h%h, 5'h%h, 32'h%h, 32'h%h, 32'h%h, 32'h%h, 2'b%b, 2'b%b, 1'b%b, 1'b%b, 2'b%b, 1'b%b, 2'b%b};", + $time, pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel); + end*/ + +endmodule + + + +// CHECKER MODULE +module selfcheck(); + reg [31:0] pc; + reg [31:0] instr; + reg [31:0] mem_addr; + reg mem_wr; + reg [31:0] mem_readdata; + reg [31:0] mem_writedata; + reg werf; + reg [4:0] alufn; + reg Z; + reg [31:0] ReadData1; + reg [31:0] ReadData2; + reg [31:0] alu_result; + reg [4:0] reg_writeaddr; + reg [31:0] reg_writedata; + reg [31:0] signImm; + reg [31:0] aluA; + reg [31:0] aluB; + reg [1:0] pcsel; + reg [1:0] wasel; + reg sext; + reg bsel; + reg [1:0] wdsel; + reg wr; + reg [1:0] asel; + +initial begin +fork +#00 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000000, 32'h201d003c, 32'h0000003c, 1'b0, 32'hxxxxxxxx, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h0000003c, 5'h1d, 32'h0000003c, 32'h0000003c, 32'h00000000, 32'h0000003c, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#01 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000004, 32'h8c040004, 32'h00000004, 1'b0, 32'h00000003, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h00000004, 5'h04, 32'h00000003, 32'h00000004, 32'h00000000, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#02 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000008, 32'h0c000005, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h0000000c, 32'h00000005, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#03 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'h23bdfff8, 32'h00000034, 1'b0, 32'hxxxxxxxx, 32'h0000003c, 1'b1, 5'b0xx01, 1'b0, 32'h0000003c, 32'h0000003c, 32'h00000034, 5'h1d, 32'h00000034, 32'hfffffff8, 32'h0000003c, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#04 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'hafbf0004, 32'h00000038, 1'b1, 32'hxxxxxxxx, 32'h0000000c, 1'b0, 5'b0xx01, 1'b0, 32'h00000034, 32'h0000000c, 32'h00000038, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h00000034, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#05 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hafa40000, 32'h00000034, 1'b1, 32'hxxxxxxxx, 32'h00000003, 1'b0, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000003, 32'h00000034, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00000034, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#06 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h28880002, 32'h00000000, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b1x011, 1'b1, 32'h00000003, 32'hxxxxxxxx, 32'h00000000, 5'h08, 32'h00000000, 32'h00000002, 32'h00000003, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#07 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h11000002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000000, 32'h00000000, 2'b01, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#08 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000030, 32'h2084ffff, 32'h00000002, 1'b0, 32'h00000000, 32'h00000003, 1'b1, 5'b0xx01, 1'b0, 32'h00000003, 32'h00000003, 32'h00000002, 5'h04, 32'h00000002, 32'hffffffff, 32'h00000003, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#09 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000034, 32'h0c000005, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h00000038, 32'h00000005, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#10 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'h23bdfff8, 32'h0000002c, 1'b0, 32'hxxxxxxxx, 32'h00000034, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000034, 32'h0000002c, 5'h1d, 32'h0000002c, 32'hfffffff8, 32'h00000034, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#11 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'hafbf0004, 32'h00000030, 1'b1, 32'hxxxxxxxx, 32'h00000038, 1'b0, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000038, 32'h00000030, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h0000002c, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#12 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hafa40000, 32'h0000002c, 1'b1, 32'hxxxxxxxx, 32'h00000002, 1'b0, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000002, 32'h0000002c, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h0000002c, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#13 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h28880002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b1x011, 1'b1, 32'h00000002, 32'h00000000, 32'h00000000, 5'h08, 32'h00000000, 32'h00000002, 32'h00000002, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#14 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h11000002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000000, 32'h00000000, 2'b01, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#15 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000030, 32'h2084ffff, 32'h00000001, 1'b0, 32'h00000000, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000002, 32'h00000002, 32'h00000001, 5'h04, 32'h00000001, 32'hffffffff, 32'h00000002, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#16 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000034, 32'h0c000005, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h00000038, 32'h00000005, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#17 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'h23bdfff8, 32'h00000024, 1'b0, 32'hxxxxxxxx, 32'h0000002c, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h0000002c, 32'h00000024, 5'h1d, 32'h00000024, 32'hfffffff8, 32'h0000002c, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#18 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'hafbf0004, 32'h00000028, 1'b1, 32'hxxxxxxxx, 32'h00000038, 1'b0, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000038, 32'h00000028, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h00000024, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#19 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hafa40000, 32'h00000024, 1'b1, 32'hxxxxxxxx, 32'h00000001, 1'b0, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000001, 32'h00000024, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00000024, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#20 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h28880002, 32'h00000001, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b1x011, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'h08, 32'h00000001, 32'h00000002, 32'h00000001, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#21 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h11000002, 32'h00000001, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b0, 32'h00000001, 32'h00000000, 32'h00000001, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000001, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#22 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000028, 32'h00041020, 32'h00000001, 1'b0, 32'h00000000, 32'h00000001, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000001, 32'h00000001, 5'h02, 32'h00000001, 32'h00001020, 32'h00000000, 32'h00000001, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#23 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000002c, 32'h08000012, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000012, 32'hxxxxxxxx, 32'h000000XX, 2'b10, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#24 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h8fbf0004, 32'h00000028, 1'b0, 32'h00000038, 32'h00000038, 1'b1, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000038, 32'h00000028, 5'h1f, 32'h00000038, 32'h00000004, 32'h00000024, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#25 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h23bd0008, 32'h0000002c, 1'b0, 32'h00000002, 32'h00000024, 1'b1, 5'b0xx01, 1'b0, 32'h00000024, 32'h00000024, 32'h0000002c, 5'h1d, 32'h0000002c, 32'h00000008, 32'h00000024, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#26 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000050, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000038, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#27 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000038, 32'h8fa40000, 32'h0000002c, 1'b0, 32'h00000002, 32'h00000001, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000001, 32'h0000002c, 5'h04, 32'h00000002, 32'h00000000, 32'h0000002c, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#28 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000003c, 32'h00441020, 32'h00000003, 1'b0, 32'h00000000, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000001, 32'h00000002, 32'h00000003, 5'h02, 32'h00000003, 32'h00001020, 32'h00000001, 32'h00000002, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#29 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000040, 32'h00441020, 32'h00000005, 1'b0, 32'h00000003, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000003, 32'h00000002, 32'h00000005, 5'h02, 32'h00000005, 32'h00001020, 32'h00000003, 32'h00000002, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#30 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000044, 32'h2042ffff, 32'h00000004, 1'b0, 32'h00000003, 32'h00000005, 1'b1, 5'b0xx01, 1'b0, 32'h00000005, 32'h00000005, 32'h00000004, 5'h02, 32'h00000004, 32'hffffffff, 32'h00000005, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#31 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h8fbf0004, 32'h00000030, 1'b0, 32'h00000038, 32'h00000038, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h00000038, 32'h00000030, 5'h1f, 32'h00000038, 32'h00000004, 32'h0000002c, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#32 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h23bd0008, 32'h00000034, 1'b0, 32'h00000003, 32'h0000002c, 1'b1, 5'b0xx01, 1'b0, 32'h0000002c, 32'h0000002c, 32'h00000034, 5'h1d, 32'h00000034, 32'h00000008, 32'h0000002c, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#33 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000050, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000038, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#34 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000038, 32'h8fa40000, 32'h00000034, 1'b0, 32'h00000003, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000002, 32'h00000034, 5'h04, 32'h00000003, 32'h00000000, 32'h00000034, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#35 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000003c, 32'h00441020, 32'h00000007, 1'b0, 32'h00000003, 32'h00000003, 1'b1, 5'b0xx01, 1'b0, 32'h00000004, 32'h00000003, 32'h00000007, 5'h02, 32'h00000007, 32'h00001020, 32'h00000004, 32'h00000003, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#36 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000040, 32'h00441020, 32'h0000000a, 1'b0, 32'hxxxxxxxx, 32'h00000003, 1'b1, 5'b0xx01, 1'b0, 32'h00000007, 32'h00000003, 32'h0000000a, 5'h02, 32'h0000000a, 32'h00001020, 32'h00000007, 32'h00000003, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#37 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000044, 32'h2042ffff, 32'h00000009, 1'b0, 32'hxxxxxxxx, 32'h0000000a, 1'b1, 5'b0xx01, 1'b0, 32'h0000000a, 32'h0000000a, 32'h00000009, 5'h02, 32'h00000009, 32'hffffffff, 32'h0000000a, 32'hffffffff, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#38 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h8fbf0004, 32'h00000038, 1'b0, 32'h0000000c, 32'h00000038, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000038, 32'h00000038, 5'h1f, 32'h0000000c, 32'h00000004, 32'h00000034, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#39 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h23bd0008, 32'h0000003c, 1'b0, 32'hxxxxxxxx, 32'h00000034, 1'b1, 5'b0xx01, 1'b0, 32'h00000034, 32'h00000034, 32'h0000003c, 5'h1d, 32'h0000003c, 32'h00000008, 32'h00000034, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#40 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000050, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h0000000c, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#41 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000000c, 32'hac020000, 32'h00000000, 1'b1, 32'h00000000, 32'h00000009, 1'b0, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000009, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00000000, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#42 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000010, 32'h08000004, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +join +end + +endmodule diff --git a/Project.srcs/sim_1/new/Project_screentest_nopause.sv b/Project.srcs/sim_1/new/Project_screentest_nopause.sv new file mode 100644 index 0000000..931dd0c --- /dev/null +++ b/Project.srcs/sim_1/new/Project_screentest_nopause.sv @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/15/2015 04:55:09 PM +// Design Name: +// Module Name: Project_screentest_nopause +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module Project_screentest_nopause( + + ); +endmodule diff --git a/Project.srcs/sim_2/new/Project_screentest_nopause.sv b/Project.srcs/sim_2/new/Project_screentest_nopause.sv new file mode 100644 index 0000000..b2a85e0 --- /dev/null +++ b/Project.srcs/sim_2/new/Project_screentest_nopause.sv @@ -0,0 +1,308 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 4/15/2015 +// +// PLEASE README! +// ============== +// +// This is a self-checking tester for your full MIPS processor +// plus memory-mapped IO. +// +// Use this tester carefully! The names of your top-level input/output +// and internal signals may be different, so modify all of signal names on the +// right-hand-side of the "wire" assigments appearing above the uut +// instantiation. Observe that the uut itself only has clock and reset inputs +// now, and no debug outputs. Also, the parameters specifying the names of the +// memory initialization files must match the actual file names. +// +// If you decide not to use some of these internal signals for debugging, you +// may comment the relevant lines out. Be sure to comment out the +// corresponding "ERROR_*" lines below as well. +// +// Finally, note that in my bitmap memory, each 12-bit color is encoded as +// RRRRGGGGBBBB (i.e., red is most significant). If you have chosen a different +// order for the red/green/blue color values, you may see ERROR signals for the +// colors light up, but there is no error if you are consistent with your +// RGB ordering. +// +////////////////////////////////////////////////////////////////////////////////// + + +module project_screentest; + + // Inputs + reg clk; + reg reset; + + // Signals inside top-level module uut + wire [31:0] pc =uut.pc; // PC + wire [31:0] instr =uut.instr; // instr coming out of instr mem + wire [31:0] mem_addr =uut.mem_addr; // addr sent to data mem + wire mem_wr =uut.mem_wr; // write enable for data mem + wire [31:0] mem_readdata =uut.mem_readdata; // data read from data mem + wire [31:0] mem_writedata =uut.mem_writedata; // write data for data mem + + // Signals inside module uut.mips + wire werf =uut.mips.werf; // WERF = write enable for register file + wire [4:0] alufn =uut.mips.alufn; // ALU function + wire Z =uut.mips.Z; // Zero flag + + // Signals inside module uut.mips.dp (datapath) + wire [31:0] ReadData1 =uut.mips.dp.ReadData1; // Reg[rs] + wire [31:0] ReadData2 =uut.mips.dp.ReadData2; // Reg[rt] + wire [31:0] alu_result =uut.mips.dp.alu_result; // ALU's output + wire [4:0] reg_writeaddr =uut.mips.dp.reg_writeaddr; // destination register + wire [31:0] reg_writedata =uut.mips.dp.reg_writedata; // write data for register file + wire [31:0] signImm =uut.mips.dp.signImm; // sign-/zero-extended immediate + wire [31:0] aluA =uut.mips.dp.aluA; // operand A for ALU + wire [31:0] aluB =uut.mips.dp.aluB; // operand B for ALU + + // Signals inside module uut.mips.c (controller) + wire [1:0] pcsel =uut.mips.c.pcsel; + wire [1:0] wasel =uut.mips.c.wasel; + wire sext =uut.mips.c.sext; + wire bsel =uut.mips.c.bsel; + wire [1:0] wdsel =uut.mips.c.wdsel; + wire wr =uut.mips.c.wr; + wire [1:0] asel =uut.mips.c.asel; + + // Signals related to module memIO (memory + memory-mapped IO) + wire [10:0] smem_addr =uut.smem_addr; // address from vgadisplaydriver to access screen mem + wire [3:0] charcode =uut.charcode; // character code returned by screen mem + wire dmem_wr =uut.io.dmem_wr; + wire smem_wr =uut.io.smem_wr; + + // Signals related to module vgadisplaydriver (display driver) + wire hsync =uut.hsync; + wire vsync =uut.vsync; + wire [3:0] red =uut.red; + wire [3:0] green =uut.green; + wire [3:0] blue =uut.blue; + wire [9:0] x =uut.displaydriver.x; + wire [9:0] y =uut.displaydriver.y; + wire [11:0] bmem_addr =uut.displaydriver.bmem_addr; + wire [11:0] bmem_color =uut.displaydriver.color; + + + // Instantiate the Unit Under Test (UUT) + top uut( + .clk(clk), + .reset(reset) + ); + +// +// CHECK ALL VALUES ABOVE THIS LINE +// YOU SHOULD NOT NEED TO MODIFY ANYTHING BELOW +// + + initial begin + // Initialize Inputs + clk = 0; + reset = 0; + end + + initial begin + #0.5 clk = 0; + forever + #0.5 clk = ~clk; + end + + initial begin + #50 $finish; + end + + + + // SELF-CHECKING CODE + + selfcheck c(); + + wire [31:0] c_pc=c.pc; + wire [31:0] c_instr=c.instr; + wire [31:0] c_mem_addr=c.mem_addr; + wire c_mem_wr=c.mem_wr; + wire [31:0] c_mem_readdata=c.mem_readdata; + wire [31:0] c_mem_writedata=c.mem_writedata; + wire c_werf=c.werf; + wire [4:0] c_alufn=c.alufn; + wire c_Z=c.Z; + wire [31:0] c_ReadData1=c.ReadData1; + wire [31:0] c_ReadData2=c.ReadData2; + wire [31:0] c_alu_result=c.alu_result; + wire [4:0] c_reg_writeaddr=c.reg_writeaddr; + wire [31:0] c_reg_writedata=c.reg_writedata; + wire [31:0] c_signImm=c.signImm; + wire [31:0] c_aluA=c.aluA; + wire [31:0] c_aluB=c.aluB; + wire [1:0] c_pcsel=c.pcsel; + wire [1:0] c_wasel=c.wasel; + wire c_sext=c.sext; + wire c_bsel=c.bsel; + wire [1:0] c_wdsel=c.wdsel; + wire c_wr=c.wr; + wire [1:0] c_asel=c.asel; + wire [10:0] c_smem_addr=c.smem_addr; + wire [3:0] c_charcode=c.charcode; + wire c_dmem_wr=c.dmem_wr; + wire c_smem_wr=c.smem_wr; + wire c_hsync=c.hsync; + wire c_vsync=c.vsync; + wire [3:0] c_red=c.red; + wire [3:0] c_green=c.green; + wire [3:0] c_blue=c.blue; + wire [9:0] c_x=c.x; + wire [9:0] c_y=c.x; + wire [11:0] c_bmem_addr=c.bmem_addr; + wire [11:0] c_bmem_color=c.bmem_color; + + + function mismatch; // some trickery needed to match two values with don't cares + input p, q; // mismatch in a bit position is ignored if q has an 'x' in that bit + integer p, q; + mismatch = (((p ^ q) ^ q) !== q); + endfunction + + wire ERROR = ERROR_pc | ERROR_instr | ERROR_mem_addr | ERROR_mem_wr | ERROR_mem_readdata + | ERROR_mem_writedata | ERROR_werf | ERROR_alufn | ERROR_Z + | ERROR_ReadData1 | ERROR_ReadData2 | ERROR_alu_result | ERROR_reg_writeaddr + | ERROR_reg_writedata | ERROR_signImm | ERROR_aluA | ERROR_aluB + | ERROR_pcsel | ERROR_wasel | ERROR_sext | ERROR_bsel | ERROR_wdsel | ERROR_wr | ERROR_asel + | ERROR_smem_addr | ERROR_charcode | ERROR_dmem_wr | ERROR_smem_wr | ERROR_hsync | ERROR_vsync + | ERROR_red | ERROR_green | ERROR_blue | ERROR_x | ERROR_y | ERROR_bmem_addr | ERROR_bmem_color; + + + wire ERROR_pc = mismatch(pc, c.pc) ? 1'bx : 1'b0; + wire ERROR_instr = mismatch(instr, c.instr) ? 1'bx : 1'b0; + wire ERROR_mem_addr = mismatch(mem_addr, c.mem_addr) ? 1'bx : 1'b0; + wire ERROR_mem_wr = mismatch(mem_wr, c.mem_wr) ? 1'bx : 1'b0; + wire ERROR_mem_readdata = mismatch(mem_readdata, c.mem_readdata) ? 1'bx : 1'b0; + wire ERROR_mem_writedata = c.mem_wr & (mismatch(mem_writedata, c.mem_writedata) ? 1'bx : 1'b0); + wire ERROR_werf = mismatch(werf, c.werf) ? 1'bx : 1'b0; + wire ERROR_alufn = mismatch(alufn, c.alufn) ? 1'bx : 1'b0; + wire ERROR_Z = mismatch(Z, c.Z) ? 1'bx : 1'b0; + wire ERROR_ReadData1 = mismatch(ReadData1, c.ReadData1) ? 1'bx : 1'b0; + wire ERROR_ReadData2 = mismatch(ReadData2, c.ReadData2) ? 1'bx : 1'b0; + wire ERROR_alu_result = mismatch(alu_result, c.alu_result) ? 1'bx : 1'b0; + wire ERROR_reg_writeaddr = c.werf & (mismatch(reg_writeaddr, c.reg_writeaddr) ? 1'bx : 1'b0); + wire ERROR_reg_writedata = c.werf & (mismatch(reg_writedata, c.reg_writedata) ? 1'bx : 1'b0); + wire ERROR_signImm = mismatch(signImm, c.signImm) ? 1'bx : 1'b0; + wire ERROR_aluA = mismatch(aluA, c.aluA) ? 1'bx : 1'b0; + wire ERROR_aluB = mismatch(aluB, c.aluB) ? 1'bx : 1'b0; + wire ERROR_pcsel = mismatch(pcsel, c.pcsel) ? 1'bx : 1'b0; + wire ERROR_wasel = c.werf & (mismatch(wasel, c.wasel) ? 1'bx : 1'b0); + wire ERROR_sext = mismatch(sext, c.sext) ? 1'bx : 1'b0; + wire ERROR_bsel = mismatch(bsel, c.bsel) ? 1'bx : 1'b0; + wire ERROR_wdsel = mismatch(wdsel, c.wdsel) ? 1'bx : 1'b0; + wire ERROR_wr = mismatch(wr, c.wr) ? 1'bx : 1'b0; + wire ERROR_asel = mismatch(asel, c.asel) ? 1'bx : 1'b0; + wire ERROR_smem_addr = mismatch(smem_addr, c.smem_addr) ? 1'bx : 1'b0; + wire ERROR_charcode = mismatch(charcode, c.charcode) ? 1'bx : 1'b0; + wire ERROR_dmem_wr = mismatch(dmem_wr, c.dmem_wr) ? 1'bx : 1'b0; + wire ERROR_smem_wr = mismatch(smem_wr, c.smem_wr) ? 1'bx : 1'b0; + wire ERROR_hsync = mismatch(hsync, c.hsync) ? 1'bx : 1'b0; + wire ERROR_vsync = mismatch(vsync, c.vsync) ? 1'bx : 1'b0; + wire ERROR_red = mismatch(red, c.red) ? 1'bx : 1'b0; + wire ERROR_green = mismatch(green, c.green) ? 1'bx : 1'b0; + wire ERROR_blue = mismatch(blue, c.blue) ? 1'bx : 1'b0; + wire ERROR_x = mismatch(x, c.x) ? 1'bx : 1'b0; + wire ERROR_y = mismatch(y, c.y) ? 1'bx : 1'b0; + wire ERROR_bmem_addr = mismatch(bmem_addr, c.bmem_addr) ? 1'bx : 1'b0; + wire ERROR_bmem_color = mismatch(bmem_color, c.bmem_color) ? 1'bx : 1'b0; + + //initial begin + // $monitor("#%02d {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h%h, 32'h%h, 32'h%h, 1'b%b, 32'h%h, 32'h%h, 1'b%b, 5'b%b, 1'b%b, 32'h%h, 32'h%h, 32'h%h, 5'h%h, 32'h%h, 32'h%h, 32'h%h, 32'h%h, 2'b%b, 2'b%b, 1'b%b, 1'b%b, 2'b%b, 1'b%b, 2'b%b};", + // $time, pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel); + // $monitor("#%02d {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h%h, 4'h%h, 1'b%b, 1'b%b, 1'b%b, 1'b%b, 4'h%h, 4'h%h, 4'h%h, 10'h%h, 10'h%h, 12'h%h, 12'h%h};", + // $time, smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color); + //end + +endmodule + + + +// CHECKER MODULE +module selfcheck(); + reg [31:0] pc; + reg [31:0] instr; + reg [31:0] mem_addr; + reg mem_wr; + reg [31:0] mem_readdata; + reg [31:0] mem_writedata; + reg werf; + reg [4:0] alufn; + reg Z; + reg [31:0] ReadData1; + reg [31:0] ReadData2; + reg [31:0] alu_result; + reg [4:0] reg_writeaddr; + reg [31:0] reg_writedata; + reg [31:0] signImm; + reg [31:0] aluA; + reg [31:0] aluB; + reg [1:0] pcsel; + reg [1:0] wasel; + reg sext; + reg bsel; + reg [1:0] wdsel; + reg wr; + reg [1:0] asel; + reg [10:0] smem_addr; + reg [3:0] charcode; + reg dmem_wr; + reg smem_wr; + reg hsync; + reg vsync; + reg [3:0] red; + reg [3:0] green; + reg [3:0] blue; + reg [9:0] x; + reg [9:0] y; + reg [11:0] bmem_addr; + reg [11:0] bmem_color; + +initial begin +fork + +#00 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000000, 32'h00000020, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b0xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'h00, 32'h00000000, 32'h00000020, 32'h00000000, 32'h00000000, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b00}; +#00 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h000, 10'h000, 12'h000, 12'hf00}; +#01 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000004, 32'h201d203c, 32'h0000203c, 1'b0, 32'hxxxxxxxx, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h0000203c, 5'h1d, 32'h0000203c, 32'h0000203c, 32'h00000000, 32'h0000203c, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#02 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000008, 32'h20040000, 32'h00000000, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b1, 32'h00000000, 32'hxxxxxxxx, 32'h00000000, 5'h04, 32'h00000000, 32'h00000000, 32'h00000000, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#03 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000000c, 32'h0c000009, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b1, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'h1f, 32'h00000010, 32'h00000009, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'b10, 1'bx, 1'bx, 2'b00, 1'b0, 2'bxx}; +#04 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000024, 32'h23bdfff8, 32'h00002034, 1'b0, 32'hxxxxxxxx, 32'h0000203c, 1'b1, 5'b0xx01, 1'b0, 32'h0000203c, 32'h0000203c, 32'h00002034, 5'h1d, 32'h00002034, 32'hfffffff8, 32'h0000203c, 32'hfffffff8, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#04 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#05 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000028, 32'hafbf0004, 32'h00002038, 1'b1, 32'hxxxxxxxx, 32'h00000010, 1'b0, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000010, 32'h00002038, 5'hxx, 32'hxxxxxxxx, 32'h00000004, 32'h00002034, 32'h00000004, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#05 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b1, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#06 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000002c, 32'hafa40000, 32'h00002034, 1'b1, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000000, 32'h00002034, 5'hxx, 32'hxxxxxxxx, 32'h00000000, 32'h00002034, 32'h00000000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#07 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000030, 32'h00042400, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'bx0010, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'h04, 32'h00000000, 32'h00002400, 32'h00000010, 32'h00000000, 2'b00, 2'b00, 1'bx, 1'b0, 2'b01, 1'b0, 2'b01}; +#07 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h001, 10'h000, 12'h001, 12'hf00}; +#08 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h002, 10'h000, 12'h002, 12'hf00}; +#08 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000034, 32'h10800002, 32'h00000000, 1'b0, 32'h00000000, 32'h00000000, 1'b0, 5'b1xx01, 1'b1, 32'h00000000, 32'h00000000, 32'h00000000, 5'hxx, 32'hxxxxxxxx, 32'h00000002, 32'h00000000, 32'h00000000, 2'b01, 2'bxx, 1'b1, 1'b0, 2'bxx, 1'b0, 2'b00}; +#09 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000040, 32'h8fa40000, 32'h00002034, 1'b0, 32'h00000000, 32'h00000000, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000000, 32'h00002034, 5'h04, 32'h00000000, 32'h00000000, 32'h00002034, 32'h00000000, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#10 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000044, 32'h8fbf0004, 32'h00002038, 1'b0, 32'h00000010, 32'h00000010, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00000010, 32'h00002038, 5'h1f, 32'h00000010, 32'h00000004, 32'h00002034, 32'h00000004, 2'b00, 2'b01, 1'b1, 1'b1, 2'b10, 1'b0, 2'b00}; +#11 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000048, 32'h23bd0008, 32'h0000203c, 1'b0, 32'hxxxxxxxx, 32'h00002034, 1'b1, 5'b0xx01, 1'b0, 32'h00002034, 32'h00002034, 32'h0000203c, 5'h1d, 32'h0000203c, 32'h00000008, 32'h00002034, 32'h00000008, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#12 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000004c, 32'h03e00008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000010, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b11, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#12 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b0, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h003, 10'h000, 12'h003, 12'hf00}; +#13 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000010, 32'h20080002, 32'h00000002, 1'b0, 32'h00000000, 32'hxxxxxxxx, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'hxxxxxxxx, 32'h00000002, 5'h08, 32'h00000002, 32'h00000002, 32'h00000000, 32'h00000002, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#14 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000014, 32'hac084000, 32'h00004000, 1'b1, 32'h00000000, 32'h00000002, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000002, 32'h00004000, 5'hxx, 32'hxxxxxxxx, 32'h00004000, 32'h00000000, 32'h00004000, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#14 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h0, 1'b0, 1'b1, 1'b1, 1'b1, 4'hf, 4'h0, 4'h0, 10'h003, 10'h000, 12'h003, 12'hf00}; +#15 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000018, 32'h20080003, 32'h00000003, 1'b0, 32'h00000000, 32'h00000002, 1'b1, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000002, 32'h00000003, 5'h08, 32'h00000003, 32'h00000003, 32'h00000000, 32'h00000003, 2'b00, 2'b01, 1'b1, 1'b1, 2'b01, 1'b0, 2'b00}; +#15 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h003, 10'h000, 12'h203, 12'h00f}; +#16 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h0000001c, 32'hac084001, 32'h00004001, 1'b1, 32'h00000001, 32'h00000003, 1'b0, 5'b0xx01, 1'b0, 32'h00000000, 32'h00000003, 32'h00004001, 5'hxx, 32'hxxxxxxxx, 32'h00004001, 32'h00000000, 32'h00004001, 2'b00, 2'bxx, 1'b1, 1'b1, 2'bxx, 1'b1, 2'b00}; +#16 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b1, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h004, 10'h000, 12'h204, 12'h00f}; +#17 {pc, instr, mem_addr, mem_wr, mem_readdata, mem_writedata, werf, alufn, Z, ReadData1, ReadData2, alu_result, reg_writeaddr, reg_writedata, signImm, aluA, aluB, pcsel, wasel, sext, bsel, wdsel, wr, asel} <= {32'h00000020, 32'h08000008, 32'hxxxxxxxx, 1'b0, 32'hxxxxxxxx, 32'h00000000, 1'b0, 5'bxxxxx, 1'bx, 32'h00000000, 32'h00000000, 32'hxxxxxxxx, 5'hxx, 32'hxxxxxxxx, 32'h00000008, 32'hxxxxxxxx, 32'h0000000X, 2'b10, 2'bxx, 1'bx, 1'bx, 2'bxx, 1'b0, 2'bxx}; +#17 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h004, 10'h000, 12'h204, 12'h00f}; +#20 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h005, 10'h000, 12'h205, 12'h00f}; +#24 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h006, 10'h000, 12'h206, 12'h00f}; +#28 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h007, 10'h000, 12'h207, 12'h00f}; +#32 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h008, 10'h000, 12'h208, 12'h00f}; +#36 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h009, 10'h000, 12'h209, 12'h00f}; +#40 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00a, 10'h000, 12'h20a, 12'h00f}; +#44 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00b, 10'h000, 12'h20b, 12'h00f}; +#48 {smem_addr, charcode, dmem_wr, smem_wr, hsync, vsync, red, green, blue, x, y, bmem_addr, bmem_color} <= {11'h000, 4'h2, 1'b0, 1'b0, 1'b1, 1'b1, 4'h0, 4'h0, 4'hf, 10'h00c, 10'h000, 12'h20c, 12'h00f}; + +join +end + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/adder.v b/Project.srcs/sources_1/imports/src/adder.v new file mode 100644 index 0000000..faa8c6e --- /dev/null +++ b/Project.srcs/sources_1/imports/src/adder.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/24/2015 12:35:21 AM +// Design Name: +// Module Name: adder +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module adder #(parameter N=32) ( + input [N-1:0] A, B, + input Cin, + output [N-1:0] Sum, + output FlagN, FlagC, FlagV + ); + + wire [N:0] carry; + assign carry[0] = Cin; + + assign FlagN = Sum[N-1]; + assign FlagC = carry[N]; + assign FlagV = carry[N] ^ carry[N-1]; + + fulladder a[N-1:0] (A, B, carry[N-1:0], Sum, carry[N:1]); + +endmodule diff --git a/Project.srcs/sources_1/imports/src/addsub.v b/Project.srcs/sources_1/imports/src/addsub.v new file mode 100644 index 0000000..1370b22 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/addsub.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/24/2015 01:42:03 PM +// Design Name: +// Module Name: addsub +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module addsub #(parameter N=32) ( + input [N-1:0] A, B, + input Subtract, + output [N-1:0] Result, + output FlagN, FlagC, FlagV + ); + + wire [N-1:0] ToBornottoB = {N{Subtract}} ^ B; + adder #(N) add(A, ToBornottoB, Subtract, Result, FlagN, FlagC, FlagV); + +endmodule diff --git a/Project.srcs/sources_1/imports/src/alu.v b/Project.srcs/sources_1/imports/src/alu.v new file mode 100644 index 0000000..6141777 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/alu.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/25/2015 10:09:21 PM +// Design Name: +// Module Name: ALU +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ALU #(parameter N=32) ( + input [N-1:0] A, B, + input [4:0] ALUfn, + output [N-1:0] R, + output FlagZ + ); + + wire subtract, bool1, bool0, shft, math; + assign {subtract, bool1, bool0, shft, math} = ALUfn[4:0]; + + // Results from the three ALU components + wire [N-1:0] addsubResult, shiftResult, logicalResult, compResult; + + addsub #(N) AS(A, B, subtract, addsubResult, FlagN, FlagC, FlagV); + shifter #(N) S(B, A[4:0], ~bool1, ~bool0, shiftResult); + logical #(N) L(A, B, {bool1, bool0}, logicalResult); + comparator #(N) C(FlagN, FlagV, FlagC, bool0, compResult); + + assign R = (~shft & math) ? addsubResult : + (shft & ~math) ? shiftResult : + (~shft & ~math) ? logicalResult : compResult; + + assign FlagZ = (R == 0); + +endmodule diff --git a/Project.srcs/sources_1/imports/src/bitmapmem.sv b/Project.srcs/sources_1/imports/src/bitmapmem.sv new file mode 100644 index 0000000..195ace1 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/bitmapmem.sv @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// The bitmap memory is a read only memory that relays the color of each pixel +// in a character to be displayed on the screen. +// +////////////////////////////////////////////////////////////////////////////////// + +`include "memory.sv" +`include "initfile.sv" +`include "display640x480.sv" + +module bitmapmem ( + input [`bmemAddrBits-1:0] addr, + output [`bmemDataBits-1:0] color + ); + + // Where bitmap memory is stored + reg [`bmemDataBits-1:0] mem [`bmemLocation-1:0]; + initial $readmemh(`bmem_init, mem, 0, `bmemLocation - 1); + + // Note the bitmap memory is readonly + assign color = mem[addr]; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/bmem_init.txt b/Project.srcs/sources_1/imports/src/bmem_init.txt new file mode 100644 index 0000000..601a8d9 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/bmem_init.txt @@ -0,0 +1,1280 @@ +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +000 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +f00 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +0f0 +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +00f +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/clockdiv.sv b/Project.srcs/sources_1/imports/src/clockdiv.sv new file mode 100644 index 0000000..cd05503 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/clockdiv.sv @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 4/6/2015 +// +////////////////////////////////////////////////////////////////////////////////// + + +module clockdivider_Nexys4(input clkin, output clk100, output clk50, output clk25, output clk12); + + MMCME2_BASE #(.CLKOUT0_DIVIDE_F(10), .CLKOUT1_DIVIDE(20), .CLKOUT2_DIVIDE(40), .CLKOUT3_DIVIDE(80), + .CLKFBOUT_MULT_F(10), .CLKIN1_PERIOD(10.0)) + mmcm (.CLKOUT0(clkout0), .CLKOUT1(clkout1), .CLKOUT2(clkout2), .CLKOUT3(clkout3), + .CLKFBOUT(clkfbout), .LOCKED(locked), .CLKIN1(clkin), .PWRDWN(1'b0), + .RST(1'b0), .CLKFBIN(clkfbin)); + + + BUFG bufclkfb (.I(clkfbout), .O(clkfbin)); + + localparam N=2; + reg [N:0] start_cnt=0; // Count 2^N clock cycles of 100 MHz clock + wire clock_enable=locked & start_cnt[N]; // Delay clock outputs by 2^N clock cycles of 100 MHz clock after lock + always_ff @(posedge clkout0) begin + if (locked & (start_cnt[N] != 1'b1)) + start_cnt <= start_cnt + 1'b1; + end + + INV I1 (.I(clock_enable), .O(not_clock_enable)); + BUFGMUX #(.CLK_SEL_TYPE("ASYNC")) buf100 (.O(clk100), .I0(clkout0), .I1(1'b0), .S(not_clock_enable)); + BUFGMUX #(.CLK_SEL_TYPE("ASYNC")) buf50 (.O(clk50), .I0(clkout1), .I1(1'b0), .S(not_clock_enable)); + BUFGMUX #(.CLK_SEL_TYPE("ASYNC")) buf25 (.O(clk25), .I0(clkout2), .I1(1'b0), .S(not_clock_enable)); + BUFGMUX #(.CLK_SEL_TYPE("ASYNC")) buf12 (.O(clk12), .I0(clkout3), .I1(1'b0), .S(not_clock_enable)); + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/comparator.v b/Project.srcs/sources_1/imports/src/comparator.v new file mode 100644 index 0000000..d91ff5d --- /dev/null +++ b/Project.srcs/sources_1/imports/src/comparator.v @@ -0,0 +1,32 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/26/2015 11:21:19 AM +// Design Name: +// Module Name: comparator +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module comparator #(parameter N=32) ( + input FlagN, FlagV, FlagC, + input bool0, + output [N-1:0] comparison + ); + + assign c = bool0 ? (~FlagC) : (FlagN ^ FlagV); + assign comparison = {{(N-1){1'b0}}, c}; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/controller.sv b/Project.srcs/sources_1/imports/src/controller.sv new file mode 100644 index 0000000..381a85b --- /dev/null +++ b/Project.srcs/sources_1/imports/src/controller.sv @@ -0,0 +1,143 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 3/26/2015 +// +////////////////////////////////////////////////////////////////////////////////// + +// These are non-R-type, so check op code +`define LW 6'b100011 +`define SW 6'b101011 +`define ADDI 6'b001000 +`define SLTI 6'b001010 +`define ORI 6'b001101 +`define BEQ 6'b000100 +`define BNE 6'b000101 +`define J 6'b000010 +`define JAL 6'b000011 +`define LUI 6'b001111 + +// These are all R-type, i.e., op=0, so check the func field +`define ADD 6'b100000 +`define SUB 6'b100010 +`define AND 6'b100100 +`define OR 6'b100101 +`define XOR 6'b100110 +`define NOR 6'b100111 +`define SLT 6'b101010 +`define SLTU 6'b101011 +`define SLL 6'b000000 +`define SLLV 6'b000100 +`define SRL 6'b000010 +`define SRA 6'b000011 +`define JR 6'b001000 + + +module controller( + input [5:0] op, + input [5:0] func, + input Z, + output [1:0] pcsel, + output [1:0] wasel, + output sext, + output bsel, + output [1:0] wdsel, + output reg [4:0] alufn, + output wr, + output werf, + output [1:0] asel + ); + + reg [9:0] controls; + assign {werf, wdsel[1:0], wasel[1:0], asel[1:0], bsel, sext, wr} = controls[9:0]; + + // Controls 4-way multiplexor + assign pcsel = ((op == 6'b0) & (func == `JR)) ? 2'b11 + : (op == `J || op == `JAL) ? 2'b10 + : ((Z && op == `BEQ) || (~Z && op == `BNE)) ? 2'b01 + : 2'b00; + + // Control Codes + // ============================================== + always_comb + + // non-R-type instructions + case(op) + `LW: controls <= 10'b1_10_01_00_1_1_0; // LW (DONE) + `SW: controls <= 10'b0_01_01_00_1_1_1; // SW (DONE) + `ADDI, // ADDI (DONE) + `SLTI, // SLTI (DONE) + `ORI: controls <= 10'b1_01_01_00_1_1_0; // ORI (DONE) + `BEQ, // BEQ (DONE) + `BNE: controls <= 10'b0_xx_xx_00_0_1_0; // BNE (DONE) + `J: controls <= 10'b0_xx_xx_xx_x_x_0; // J (DONE) + `JAL: controls <= 10'b1_00_10_xx_x_x_0; // JAL (DONE) + `LUI: controls <= 10'b1_01_01_10_1_0_1; // LUI (DONE) + + // R-type + 6'b000000: + case(func) + `ADD, // ADD (DONE) + `SUB, // SUB (DONE) + `AND, // AND (DONE) + `OR, // OR (DONE) + `XOR, // XOR (DONE) + `NOR, // NOR (DONE) + `SLT, // SLT (DONE) + `SLTU: controls <= 10'b1_01_00_00_0_x_0; // SLTU (DONE) + `SLL, // SLL (DONE) + `SRL, // SRL (DONE) + `SRA: controls <= 10'b1_01_00_01_0_x_0; // SRA (DONE) + `SLLV: controls <= 10'b1_01_00_00_0_x_0; // SLLV (DONE) + `JR: controls <= 10'b0_xx_xx_xx_x_x_0; // JR (DONE) + + // unknown instruction, turn off register and memory writes + default: controls <= 10'b0_00_00_00_0_0_0; // ??? (DONE) + + endcase + + // unknown instruction, turn off register and memory writes + default: controls <= 10'b0_00_00_00_0_0_0; // ??? (DONE) + + endcase + + // ALUFN Codes + // ============================================== + always_comb + + // non-R-type instructions + case(op) + `LW, // LW (DONE) + `SW, // SW (DONE) + `ADDI: alufn <= 5'b0xx01; // ADDI (DONE) + `SLTI: alufn <= 5'b1x011; // SLTI (DONE) + `BEQ, // BEQ (DONE) - Want to see if Z flag is 0 + `BNE: alufn <= 5'b1xx01; // BNE (DONE) + `LUI: alufn <= 5'bx0010; // LUI (DONE) + + // R-type + 6'b000000: + case(func) + `ADD: alufn <= 5'b0xx01; // ADD (DONE) + `SUB: alufn <= 5'b1xx01; // SUB (DONE) + `AND: alufn <= 5'bx0000; // AND (DONE) + `OR: alufn <= 5'bx0100; // OR (DONE) + `XOR: alufn <= 5'bx1000; // XOR (DONE) + `NOR: alufn <= 5'bx1100; // NOR (DONE) + `SLT: alufn <= 5'b1x011; // SLT (DONE) + `SLTU: alufn <= 5'b1x111; // SLTU (DONE) + `SLL, // SLL (DONE) + `SLLV: alufn <= 5'bx0010; // SLLV (DONE) + `SRL: alufn <= 5'bx1010; // SRL (DONE) + `SRA: alufn <= 5'bx1110; // SRA (DONE) + + default: alufn <= 5'bxxxxx; // ??? (DONE) + + endcase + + default: alufn <= 5'bxxxxx; // ??? (DONE) + + endcase + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/datapath.sv b/Project.srcs/sources_1/imports/src/datapath.sv new file mode 100644 index 0000000..e64561e --- /dev/null +++ b/Project.srcs/sources_1/imports/src/datapath.sv @@ -0,0 +1,111 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/04/2015 04:24:30 AM +// Design Name: +// Module Name: datapath +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module datapath #( + parameter Abits = 5, // Number of bits in address + parameter Dbits = 32, // Number of bits in data + parameter Nloc = 32 // Number of memory locations +)( + input clk, + input reset, + output reg [31:0] pc = 0, + input [31:0] instr, + input [1:0] pcsel, + input [1:0] wasel, + input sext, + input bsel, + input [1:0] wdsel, + input [4:0] alufn, + input werf, + input [1:0] asel, + output Z, + output [31:0] mem_addr, + output [31:0] mem_writedata, + input [31:0] mem_readdata +); + + wire [4:0] shamt; + wire [31:0] pcPlus4; + wire [31:0] signImm; + wire [31:0] J, JT, BT; + wire [4:0] Rs, Rt, Rd; + wire [31:0] ReadData1, ReadData2; + wire [31:0] alu_result, aluA, aluB; + wire [31:0] reg_writeaddr, reg_writedata; + + + // Program Counter + // ============================================= + + assign pcPlus4 = pc + 4; + + always_ff @(posedge clk) begin + if(reset) pc <= 0; + else pc <= (pcsel == 2'b11) ? JT + : (pcsel == 2'b10) ? {pc[31:28], J, 2'b00} + : (pcsel == 2'b01) ? BT + : pcPlus4; + end + + + // Branching/Jumping + // ============================================= + + assign JT = ReadData1; + assign J = instr[25:0]; + assign BT = pcPlus4 + (signImm << 2); + + + // Register File + // ============================================= + + assign Rs = instr[25:21]; + assign Rt = instr[20:16]; + assign Rd = instr[15:11]; + assign reg_writeaddr = (wasel == 2'b00) ? Rd : (wasel == 2'b01) ? Rt : 31; + assign reg_writedata = (wdsel == 2'b00) ? pcPlus4 : (wdsel == 2'b01) ? alu_result : mem_readdata; + + register_file #(Abits, Dbits, Nloc) rf( + clk, werf, Rs, Rt, reg_writeaddr, + reg_writedata, ReadData1, ReadData2 + ); + + + // Sign Extension + // ============================================= + + signExtension signExt(sext, instr[15:0], signImm); + + + // ALU + // ============================================= + + assign aluA = (asel == 2'b00) ? ReadData1 : (asel == 2'b01) ? shamt : 16; + assign aluB = (bsel == 1'b0) ? ReadData2 : signImm; + assign mem_writedata = ReadData2; + assign mem_addr = alu_result; + assign shamt = instr[10:6]; + + ALU #(Dbits) alu(aluA, aluB, alufn, alu_result, Z); + + +endmodule diff --git a/Project.srcs/sources_1/imports/src/debouncer.sv b/Project.srcs/sources_1/imports/src/debouncer.sv new file mode 100644 index 0000000..d3350b9 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/debouncer.sv @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// Since button presses may bounce, we ensure the value emitted doesn't osscilate +// too rapidly. If it stays the same for a long enough time (as described below), +// we retain the button value as either pressed or released. +// +////////////////////////////////////////////////////////////////////////////////// + + +module debouncer( + input raw, + input clk, + input invert, + output clean + ); + + // Set N for debounce duration of 10ms + // Since clock runs at 100 MHz or 10^8 cycles per second + // So then it runs 10^6 cycles per 10 ms ~ 2^20. + localparam N = 20; + reg [N:0] count; + + // Used to hold clean value before inversion + reg tmp_clean = 0; + always_ff @(posedge clk) begin + count <= (raw != tmp_clean) ? count + 1 : 0; + tmp_clean <= (count[N] == 1) ? raw : tmp_clean; + end + + // Allows inversion (for when simulating and actually running) + assign clean = tmp_clean ^ invert; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/display640x480.sv b/Project.srcs/sources_1/imports/src/display640x480.sv new file mode 100644 index 0000000..b9276e5 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/display640x480.sv @@ -0,0 +1,58 @@ +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter (Revised from Montek Singh) +// 4/15/2015 +// +// Properties related to the VGA display driver. These include custom made +// characters (in which color data is stored in bitmap memory). +// +////////////////////////////////////////////////////////////////////////////////// + + +// Frame Properties +// =========================================== + +`define WholeLine 800 // x lies in [0..WholeLine-1] +`define WholeFrame 525 // y lies in [0..WholeFrame-1] + +`define xbits $clog2(`WholeLine) // how many bits needed to count x? +`define ybits $clog2(`WholeFrame) // how many bits needed to count y? + + +// Horizontal/Vertical Syncs +// =========================================== + +`define hFrontPorch 16 +`define hBackPorch 48 +`define hSyncPulse 96 +`define vFrontPorch 10 +`define vBackPorch 33 +`define vSyncPulse 2 + +`define hSyncPolarity 1'b1 +`define vSyncPolarity 1'b1 + +`define hSyncStart (`WholeLine - `hBackPorch - `hSyncPulse) +`define hSyncEnd (`hSyncStart + `hSyncPulse - 1) +`define vSyncStart (`WholeFrame - `vBackPorch - `vSyncPulse) +`define vSyncEnd (`vSyncStart + `vSyncPulse - 1) + +`define hVisible (`WholeLine - `hFrontPorch - `hSyncPulse - `hBackPorch) +`define vVisible (`WholeFrame - `vFrontPorch - `vSyncPulse - `vBackPorch) + + +// Character Properties +// =========================================== + +`define charSize 256 // (charWidth * charHeight) +`define charWidth 16 +`define charHeight 16 +`define charRowCount 30 // (480 / charHeight) +`define charColCount 40 // (640 / charWidth) + + +// Character Convenience Properties +// =========================================== + +`define charWidthShift $clog2(`charWidth) +`define charHeightShift $clog2(`charHeight) diff --git a/Project.srcs/sources_1/imports/src/display8digit.sv b/Project.srcs/sources_1/imports/src/display8digit.sv new file mode 100644 index 0000000..c8e4ac4 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/display8digit.sv @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Engineer: Montek Singh +// +// Create Date: 2/11/2015 +////////////////////////////////////////////////////////////////////////////////// + +module display8digit( + input [31:0] val, + input clock, + output [7:0] segments, + output [7:0] digitselect + ); + + reg [31:0] counter = 0; + wire [2:0] topthree; + wire [3:0] value4bit; + + always_ff @(posedge clock) + counter <= counter + 1'b1; + + assign topthree[2:0] = counter[17:15]; + // assign toptwo[1:0] = counter[23:22]; // Try this instead to slow things down! + + + assign digitselect[7:0] = ~ ( topthree == 3'b000 ? 8'b00000001 // Note inversion + : topthree == 3'b001 ? 8'b00000010 + : topthree == 3'b010 ? 8'b00000100 + : topthree == 3'b011 ? 8'b00001000 + : topthree == 3'b100 ? 8'b00010000 + : topthree == 3'b101 ? 8'b00100000 + : topthree == 3'b110 ? 8'b01000000 + : 8'b10000000 ); + + assign value4bit = ( topthree == 3'b000 ? val[3:0] + : topthree == 3'b001 ? val[7:4] + : topthree == 3'b010 ? val[11:8] + : topthree == 3'b011 ? val[15:12] + : topthree == 3'b100 ? val[19:16] + : topthree == 3'b101 ? val[23:20] + : topthree == 3'b110 ? val[27:24] + : val[31:29] ); + + hexto7seg myhexencoder(value4bit, segments); + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/dmem.sv b/Project.srcs/sources_1/imports/src/dmem.sv new file mode 100644 index 0000000..ae2a733 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/dmem.sv @@ -0,0 +1,37 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// Contains the data memory (data that is stored and loaded by MIPS). This allows +// saving state by the computer and restoring state at a later time. +// +////////////////////////////////////////////////////////////////////////////////// + +`include "memory.sv" +`include "initfile.sv" + +module dmem ( + input clk, + input mem_wr, + input [31:0] mem_addr, + input [31:0] mem_writedata, + output [31:0] mem_readdata + ); + + // Initialize Memory + // Note we want to derive a word address so + // mem_addr is shifted right by 2 + reg [`dmemDataBits-1:0] mem [`dmemLocation-1:0]; + initial $readmemh(`dmem_init, mem, 0, `dmemLocation - 1); + + // Allow Saving Data + always_ff @(posedge clk) + if(mem_wr) + mem[{2'b00, mem_addr[31:2]}] <= mem_writedata; + + // Allow Reading Data + assign mem_readdata = mem[{2'b00, mem_addr[31:2]}]; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/dmem_init.txt b/Project.srcs/sources_1/imports/src/dmem_init.txt new file mode 100644 index 0000000..72cf8de --- /dev/null +++ b/Project.srcs/sources_1/imports/src/dmem_init.txt @@ -0,0 +1 @@ +0 // data memory not used in this program \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/fulladder.v b/Project.srcs/sources_1/imports/src/fulladder.v new file mode 100644 index 0000000..f47d8f7 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/fulladder.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/09/2015 03:24:32 PM +// Design Name: +// Module Name: fulladder +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module fulladder( + input A, + input B, + input Cin, + output Sum, + output Cout + ); + + assign Sum = Cin ^ A ^ B; + assign Cout = (Cin & (A ^ B)) | (A & B); + +endmodule diff --git a/Project.srcs/sources_1/imports/src/hexto7seg.sv b/Project.srcs/sources_1/imports/src/hexto7seg.sv new file mode 100644 index 0000000..e029d47 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/hexto7seg.sv @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 2/3/2015 +// +////////////////////////////////////////////////////////////////////////////////// + +module hexto7seg( + input [3:0] X, + output reg [7:0] segments + ); + + always_comb begin + case (X) + 4'h0: segments <= ~8'b11111100; + 4'h1: segments <= ~8'b01100000; + 4'h2: segments <= ~8'b11011010; + 4'h3: segments <= ~8'b11110010; + 4'h4: segments <= ~8'b01100110; + 4'h5: segments <= ~8'b10110110; + 4'h6: segments <= ~8'b10111110; + 4'h7: segments <= ~8'b11100000; + 4'h8: segments <= ~8'b11111110; + 4'h9: segments <= ~8'b11110110; + 4'hA: segments <= ~8'b11101110; + 4'hB: segments <= ~8'b00111110; + 4'hC: segments <= ~8'b10011100; + 4'hD: segments <= ~8'b01111010; + 4'hE: segments <= ~8'b10011110; + 4'hF: segments <= ~8'b10001110; + default: segments <= ~8'b00000001; + endcase + end + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/imem.sv b/Project.srcs/sources_1/imports/src/imem.sv new file mode 100644 index 0000000..f187dad --- /dev/null +++ b/Project.srcs/sources_1/imports/src/imem.sv @@ -0,0 +1,29 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// Contains the instructions (hex dumped by the MARS assembler probably). Note this +// is also a readonly memory. In addition, word addresses are accessed so we shift +// the program counter by 2 bits (since every 4 count corresponds to a word) +// +////////////////////////////////////////////////////////////////////////////////// + +`include "memory.sv" +`include "initfile.sv" + +module imem ( + input [31:0] pc, + output [31:0] instr +); + + // Initialize Memory + reg [`imemDataBits-1:0] mem [`imemLocation-1:0]; + initial $readmemh(`imem_init, mem, 0, `imemLocation - 1); + + // Return the instruction at PC + // Note we want to derive a word address so shift right by 2 + assign instr = mem[{2'b00, pc[31:2]}]; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/imem_init.txt b/Project.srcs/sources_1/imports/src/imem_init.txt new file mode 100644 index 0000000..f6fee7a --- /dev/null +++ b/Project.srcs/sources_1/imports/src/imem_init.txt @@ -0,0 +1,128 @@ +00000020 +201d203c +20100001 +20110028 +2012026c +20130029 +201403be +20150075 +20160072 +20170029 +200f0004 +8c086000 +1517fffe +20040014 +0c000075 +200404b0 +0c00001b +0c000030 +0c00004c +0c00005a +0c000025 +0c000068 +14400001 +0800000d +8c086000 +1517ffe8 +08000018 +23bdfffc +afa40000 +000f4020 +2084ffff +20894000 +ad280000 +1480fffc +8fa40000 +23bd0004 +03e00008 +22680000 +22890000 +200a0006 +ad004000 +ad204000 +21080028 +21290028 +214affff +1540fffa +ae404000 +03e00008 +02507020 +01d17020 +20080007 +00134820 +00145020 +11c90006 +11ca0005 +21290028 +214a0028 +2108ffff +1500fffa +08000043 +00108022 +0010402a +11000001 +08000042 +200f0001 +08000043 +200f0002 +000e402a +11000003 +200804b0 +010e402a +11000001 +00118822 +02509020 +02519020 +03e00008 +20040000 +0254402a +11000007 +08000052 +0284a020 +03e00008 +2008004e +1288fffc +2004ffd8 +08000050 +200803be +1288fff8 +20040028 +08000050 +20040000 +8c086000 +11150003 +11160006 +02649820 +03e00008 +20080029 +1268fffc +2004ffd8 +0800005e +20080399 +1268fff8 +20040028 +0800005e +20020000 +2008001d +20090000 +200a0027 +12490006 +124a0005 +2108ffff +21290028 +214a0028 +1500fffa +08000074 +20420001 +03e00008 +23bdfff8 +afbf0004 +afa40000 +00042400 +10800002 +2084ffff +1480fffe +8fa40000 +8fbf0004 +23bd0008 +03e00008 diff --git a/Project.srcs/sources_1/imports/src/initfile.sv b/Project.srcs/sources_1/imports/src/initfile.sv new file mode 100644 index 0000000..a42a144 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/initfile.sv @@ -0,0 +1,19 @@ +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// Initialization files used to fill up respectively: +// 1) Instruction Memory +// 2) Data Memory +// 3) Screen Memory +// 4) Bitmap Memory +// 5) Register File +// +////////////////////////////////////////////////////////////////////////////////// + +`define imem_init "imem_init.txt" +`define dmem_init "dmem_init.txt" +`define smem_init "smem_init.txt" +`define bmem_init "bmem_init.txt" +`define regd_init "regd_init.txt" diff --git a/Project.srcs/sources_1/imports/src/keyboard.sv b/Project.srcs/sources_1/imports/src/keyboard.sv new file mode 100644 index 0000000..7f3ca4e --- /dev/null +++ b/Project.srcs/sources_1/imports/src/keyboard.sv @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps + +// Montek Singh +// April 8, 2015 + + +module keyboard( + input clk, + input ps2_clk, + input ps2_data, + output reg [23:0] keyb_char = 0 + ); + + reg [9:0] bits = 0; + reg [3:0] count = 0; + reg [1:0] ps2_clk_prev2 = 2'b11; + reg [19:0] timeout = 0; + + always_ff @(posedge clk) + ps2_clk_prev2 <= {ps2_clk_prev2[0], ps2_clk}; + + always_ff @(posedge clk) + begin + if((count == 11) || (timeout[19] == 1)) + begin + count <= 0; + if((keyb_char[7:0] == 8'hE0) || (keyb_char[7:0] == 8'hF0)) + keyb_char[23:0] <= {keyb_char[15:0], bits[7:0]}; + else + keyb_char[23:0] <= {16'b0, bits[7:0]}; + end + else + begin + if(ps2_clk_prev2 == 2'b10) + begin + count <= count + 1; + bits <= {ps2_data, bits[9:1]}; + end + end + end + + always_ff @(posedge clk) + timeout <= (count != 0) ? timeout + 1 : 0; + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/logical.v b/Project.srcs/sources_1/imports/src/logical.v new file mode 100644 index 0000000..9b1d1d7 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/logical.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/24/2015 02:17:22 PM +// Design Name: +// Module Name: logical +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module logical #(parameter N=32) ( + input [N-1:0] A, B, + input [1:0] op, + output [N-1:0] R + ); + + assign R = (op == 2'b00) ? A & B : + (op == 2'b01) ? A | B : + (op == 2'b10) ? A ^ B : + (op == 2'b11) ? ~(A | B) : {N{1'b1}}; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/memIO.sv b/Project.srcs/sources_1/imports/src/memIO.sv new file mode 100644 index 0000000..321342b --- /dev/null +++ b/Project.srcs/sources_1/imports/src/memIO.sv @@ -0,0 +1,113 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// Contains all memory mapped IO, including the screen, data memory, keyboard, +// input in general, and the memory mapper. It will relay the correct readdata +// out to the mips processor (as it must be able to distinguish between the +// different memories depending on the given address), and the character code +// for the VGA display adapter. +// +////////////////////////////////////////////////////////////////////////////////// + +`include "memory.sv" +`include "display640x480.sv" + +module memIO ( + input clk, + input ps2_clk, + input ps2_data, + input mips_wr, + input [31:0] mips_addr, + input [31:0] mips_writedata, + output [31:0] mips_readdata, + input [`smemAddrBits-1:0] driver_addr, + output [`smemDataBits-1:0] driver_readdata, + output [7:0] segments, digitselect + ); + + // Wiring + // =========================================== + + wire dmem_wr, dmem_active; + wire [`dmemAddrBits-1:0] dmem_addr; + wire [`dmemDataBits-1:0] dmem_readdata; + wire [`dmemDataBits-1:0] dmem_writedata; + + wire smem_wr, smem_active; + wire [`smemAddrBits-1:0] smem_addr; + wire [`smemDataBits-1:0] smem_readdata; + wire [`smemDataBits-1:0] smem_writedata; + + wire kmem_active; + wire [`kmemDataBits-1:0] kmem_readdata; + + + // Active Memory + // =========================================== + // Convenience wires determining which memory to read from and write to + + assign smem_active = (mips_addr >= `smemLow && mips_addr <= `smemHigh); + assign dmem_active = (mips_addr >= `dmemLow && mips_addr <= `dmemHigh); + assign kmem_active = (mips_addr == `kmemLow); + + + // Addressing + // =========================================== + // This just requires offsetting the address by the base amount + + assign smem_addr = mips_addr - `smemLow; + assign dmem_addr = mips_addr - `dmemLow; + + + // Read Data + // =========================================== + // Determine which is read depending on the address location being accessed + // Note charCode is a smaller bus than dmem_readdata, which has size equal mem_readdata + // Returns the read data back to the MIPS processor + + assign mips_readdata = smem_active ? {{(`word-`smemDataBits){1'b0}}, smem_readdata} : + dmem_active ? {{(`word-`dmemDataBits){1'b0}}, dmem_readdata} : + kmem_active ? {{(`word-`kmemDataBits){1'b0}}, kmem_readdata} : + 32'h00000000; + + + // Write Data + // =========================================== + // Determines if writing out to screen or data (if at all) + // Note the writedata should just be propagated to all other write datas + + assign dmem_wr = dmem_active ? mips_wr : 0; + assign smem_wr = smem_active ? mips_wr : 0; + + + // Keyboard Memory + // =========================================== + // Note the keyboard cannot be written to. It is merely read. + + keyboard kmem(clk, ps2_clk, ps2_data, kmem_readdata); + display8digit disp(kmem_readdata, clk, segments, digitselect); + + + // Screen Memory + // =========================================== + // Data to be displayed on the monitor. Note this has two ports + // for reading (one for VGA driver and the other for MIPS accessing) + // and one port for writing + + smem smem(.clk(clk), .wr(smem_wr), + .readaddr1(driver_addr), .readaddr2(smem_addr), + .writeaddr(smem_addr), .writedata(mips_writedata), + .charcode1(driver_readdata), .charcode2(smem_readdata)); + + + // Data Memory + // =========================================== + // Data to be loaded or written to + + dmem dmem(clk, dmem_wr, dmem_addr, mips_writedata, dmem_readdata); + + +endmodule diff --git a/Project.srcs/sources_1/imports/src/memory.sv b/Project.srcs/sources_1/imports/src/memory.sv new file mode 100644 index 0000000..ce8f8df --- /dev/null +++ b/Project.srcs/sources_1/imports/src/memory.sv @@ -0,0 +1,66 @@ +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// All definitions revolving around memories (or possibly memory mapped IOs). +// +////////////////////////////////////////////////////////////////////////////////// + + +// MIPs Architecture +// =========================================== +// MIPs works via a 32-bit word. All instructions, results, etc. +// must be aligned on a word (and probably sign extended to 32 bits) + +`define word 32 + +// Starting and ending addresses of memory sections as defined by +// the MARS assembler. + +`define dmemLow 32'h0000_2000 +`define dmemHigh 32'h0000_3FFF +`define smemLow 32'h0000_4000 +`define smemHigh 32'h0000_4FFF +`define kmemLow 32'h0000_6000 + + +// Instruction Memory +// =========================================== + +`define imemAddrBits 32 +`define imemDataBits 32 +`define imemLocation 256 + + +// Data Memory +// =========================================== + +`define dmemAddrBits 32 +`define dmemDataBits 32 +`define dmemLocation 32 + + +// Screen Properties +// =========================================== + +`define smemDataBits 8 +`define smemAddrBits $clog2(`smemLocation) +`define smemLocation 1200 + + +// Bitmap Properties +// =========================================== +// Note data bits need to be 12 since RGB is 12 bits long +// and locations is (`charWidth * `charHeight * `charUniqueCount) + +`define bmemDataBits 12 +`define bmemAddrBits $clog2(`bmemLocation) +`define bmemLocation 1280 + + +// Keyboard Properties +// =========================================== +// Note the keyboard's address bit just needs to be greater than `kmemLow + +`define kmemDataBits 24 diff --git a/Project.srcs/sources_1/imports/src/mips.sv b/Project.srcs/sources_1/imports/src/mips.sv new file mode 100644 index 0000000..47a3281 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/mips.sv @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 3/26/2015 +// +////////////////////////////////////////////////////////////////////////////////// + +module mips( + input clk, + input reset, + output [31:0] pc, + input [31:0] instr, + output mem_wr, + output [31:0] mem_addr, + output [31:0] mem_writedata, + input [31:0] mem_readdata + ); + + wire [1:0] pcsel, wdsel, wasel; + wire [4:0] alufn; + wire Z, sext, bsel, dmem_wr, werf; + wire [1:0] asel; + + controller c(.op(instr[31:26]), .func(instr[5:0]), .Z(Z), + .pcsel(pcsel), .wasel(wasel[1:0]), .sext(sext), .bsel(bsel), + .wdsel(wdsel), .alufn(alufn), .wr(mem_wr), .werf(werf), .asel(asel)); + + datapath #(5, 32, 32) dp(.clk(clk), .reset(reset), + .pc(pc), .instr(instr), + .pcsel(pcsel), .wasel(wasel[1:0]), .sext(sext), .bsel(bsel), + .wdsel(wdsel), .alufn(alufn), .werf(werf), .asel(asel), + .Z(Z), .mem_addr(mem_addr), .mem_writedata(mem_writedata), .mem_readdata(mem_readdata)); + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/regd_init.txt b/Project.srcs/sources_1/imports/src/regd_init.txt new file mode 100644 index 0000000..463fdf1 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/regd_init.txt @@ -0,0 +1,32 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/register_file.sv b/Project.srcs/sources_1/imports/src/register_file.sv new file mode 100644 index 0000000..4c2af06 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/register_file.sv @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Montek Singh +// 3/18/2015 +// +////////////////////////////////////////////////////////////////////////////////// + +`include "initfile.sv" + +module register_file #( + parameter Abits = 5, + parameter Dbits = 32, + parameter Nloc = 32 +)( + input clock, wr, // WriteEnable: if wr==1, data is written into mem + input [Abits-1 : 0] ReadAddr1, ReadAddr2, WriteAddr, // 3 addresses + input [Dbits-1 : 0] WriteData, // Data for writing into register file (if wr==1) + output [Dbits-1 : 0] ReadData1, ReadData2 // 2 output ports + ); + + // Initialize Memory + reg [Dbits-1 : 0] rf [Nloc - 1 : 0]; + initial $readmemh(`regd_init, rf, 0, Nloc - 1); + + // Memory write: only when wr==1, and only at posedge clock + always_ff @(posedge clock) + if(wr) + rf[WriteAddr] <= WriteData; + + // When accessing register 0, always return 0 + assign ReadData1 = (ReadAddr1 == 0) ? 0 : rf[ReadAddr1]; + assign ReadData2 = (ReadAddr2 == 0) ? 0 : rf[ReadAddr2]; + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/shifter.v b/Project.srcs/sources_1/imports/src/shifter.v new file mode 100644 index 0000000..5e6702f --- /dev/null +++ b/Project.srcs/sources_1/imports/src/shifter.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/25/2015 09:43:36 PM +// Design Name: +// Module Name: shifter +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module shifter #(parameter N=32) ( + input signed [N-1:0] IN, + input [$clog2(N)-1:0] shamt, // ceiling log base 2 + input left, input logical, + output [N-1:0] OUT + ); + + assign OUT = left ? (IN << shamt) : + (logical ? IN >> shamt : IN >>> shamt); + +endmodule diff --git a/Project.srcs/sources_1/imports/src/signExtension.sv b/Project.srcs/sources_1/imports/src/signExtension.sv new file mode 100644 index 0000000..3ebfe37 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/signExtension.sv @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/04/2015 05:06:21 AM +// Design Name: +// Module Name: sext +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module signExtension( + input en, + input [15:0] imm, + output [31:0] signImm + ); + + assign signImm = en ? {{16{imm[15]}}, imm} : {{16{32'h00}}, imm}; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/smem.sv b/Project.srcs/sources_1/imports/src/smem.sv new file mode 100644 index 0000000..40a6b46 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/smem.sv @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/08/2015 10:44:13 AM +// Design Name: +// Module Name: screenmem +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`include "memory.sv" +`include "initfile.sv" + +module smem ( + input clk, input wr, + input [`smemAddrBits-1:0] readaddr1, + input [`smemAddrBits-1:0] readaddr2, + input [`smemAddrBits-1:0] writeaddr, + input [`smemDataBits-1:0] writedata, + output [`smemDataBits-1:0] charcode1, + output [`smemDataBits-1:0] charcode2 + ); + + // Where screen memory is stored + reg [`smemDataBits-1:0] mem [`smemLocation-1:0]; + initial $readmemh(`smem_init, mem, 0, `smemLocation - 1); + + // Memory write: only when wr==1, and only at posedge clock + always_ff @(posedge clk) + if(wr) + mem[writeaddr] <= writedata; + + // Returns the charcode which indexes bitmap memory + assign charcode1 = mem[readaddr1]; + assign charcode2 = mem[readaddr2]; + +endmodule diff --git a/Project.srcs/sources_1/imports/src/smem_init.txt b/Project.srcs/sources_1/imports/src/smem_init.txt new file mode 100644 index 0000000..902e18d --- /dev/null +++ b/Project.srcs/sources_1/imports/src/smem_init.txt @@ -0,0 +1,1200 @@ +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 +04 \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/top.v b/Project.srcs/sources_1/imports/src/top.v new file mode 100644 index 0000000..4f16c31 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/top.v @@ -0,0 +1,100 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter (Revised from Montek Singh) +// 3/26/2015 +// +// This is the topmost module that ties all IO devices with the MIPs processor. +// It allows mips assembly code (hex dumped by the MARs assembler for example) +// to be run. +// +// Note when writing code, screen memory is at 0x00004000 and data memory is +// at 0x00002000, so store data at these locations for expected changes to occur. +// +////////////////////////////////////////////////////////////////////////////////// + +`include "memory.sv" +`include "initfile.sv" +`include "display640x480.sv" + +module top ( + input clk, reset, + input ps2_clk, ps2_data, + output hsync, vsync, + output [3:0] red, green, blue, + output [7:0] segments, digitselect + ); + + // Wiring + // =========================================== + + // Instruction Memory & MIPS + wire mem_wr, c_reset; + wire [31:0] pc, instr, mem_readdata, mem_writedata, mem_addr; + + // Memory IO + wire [`smemDataBits-1:0] charcode; + wire [`smemAddrBits-1:0] smem_addr; + + // Clocks + wire clk100, clk50, clk25, clk12; + + + // Clocking + // =========================================== + + // Uncomment *only* one of the following two lines: + // when synthesizing, use the first line + // when simulating, get rid of the clock divider, and use the second line + clockdivider_Nexys4 clkdv(clk, clk100, clk50, clk25, clk12); + //assign clk100=clk; assign clk50=clk; assign clk25=clk; assign clk12=clk; + + + // Instruction Storage + // =========================================== + // Instructions will be stored at 0x0000 and data stored at 0x2000 + // This happens with the MARS assembler set at "Compact, Text at 0" + + imem imem(pc, instr); + + + // MIPS + // =========================================== + // Processes the instructions stored in the instruction memory. + // Note the reset is high if the button is UP, not when it is down. + // So we must invert this; during simulations we then set reset to high + + // We modify the debouncer slightly. If simulating, maintain an inversion + // of 0. Otherwise, set inversion to 1 (since reset is high when depressed). + //debouncer rbouncer(reset, clk12, 0, c_reset); + debouncer rbouncer(reset, clk12, 1, c_reset); + + mips mips(.clk(clk12), .reset(c_reset), .pc(pc), + .instr(instr), .mem_wr(mem_wr), .mem_addr(mem_addr), + .mem_writedata(mem_writedata), .mem_readdata(mem_readdata)); + + + // Memory IO + // =========================================== + // Takes in the MIPS instruction and writes to data and memory + // Also takes in a screen address and returns a character code + // to be displayed at the corresponding address + + memIO io(.clk(clk12), .ps2_clk(ps2_clk), .ps2_data(ps2_data), + .mips_wr(mem_wr), .mips_addr(mem_addr), + .mips_writedata(mem_writedata), .mips_readdata(mem_readdata), + .driver_addr(smem_addr), .driver_readdata(charcode), + .segments(segments), .digitselect(digitselect)); + + + // VGA Display Driver + // =========================================== + // These contain bitmap information (which is readonly) and outputs color + // based on the given character from memory IO + + vgadisplaydriver displaydriver( + .clk(clk100), .charcode(charcode), .hsync(hsync), .vsync(vsync), + .red(red), .green(green), .blue(blue), .smem_addr(smem_addr)); + + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv b/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv new file mode 100644 index 0000000..3ff76f8 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/vgadisplaydriver.sv @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// The display driver relates the memory mapped IO to the bitmap memory, and relays +// which color to display at which screen address. +// +////////////////////////////////////////////////////////////////////////////////// + +`include "memory.sv" +`include "display640x480.sv" + +module vgadisplaydriver ( + input clk, + input [`smemDataBits-1:0] charcode, + output hsync, vsync, + output [3:0] red, green, blue, + output [`smemAddrBits-1:0] smem_addr + ); + + // VGA Display + // =========================================== + // Loop through all columns and rows of the VGA display + + wire [`xbits-1:0] x; + wire [`ybits-1:0] y; + + vgatimer timer(clk, hsync, vsync, activevideo, x, y); + + + // Screen Memory + // =========================================== + // Note the screen address corresponds to the index of the character being + // accessed, and not necessarily the (x, y) pixel coordinates we are looking at + + assign smem_addr = (x >> `charWidthShift) + ((y >> `charHeightShift) * `charColCount); + + + // Bitmap Memory + // =========================================== + // The bitmap character returned is the offset of the character given + // by the current (x, y) coordinate + + wire [`bmemDataBits-1:0] color; + wire [`bmemAddrBits-1:0] bmem_addr; + + assign bmem_addr = (`charSize * charcode) + (x % `charWidth + ((y % `charHeight) * `charWidth)); + bitmapmem bmem(bmem_addr, color); + + + // Display Adapter + // =========================================== + // Note the Nexys 4 VGA adapter requires 4 bits of data for each + // color component. + + assign red[3:0] = (activevideo == 1) ? color[11:8] : 4'b0; + assign green[3:0] = (activevideo == 1) ? color[7:4] : 4'b0; + assign blue[3:0] = (activevideo == 1) ? color[3:0] : 4'b0; + + +endmodule \ No newline at end of file diff --git a/Project.srcs/sources_1/imports/src/vgatimer.sv b/Project.srcs/sources_1/imports/src/vgatimer.sv new file mode 100644 index 0000000..b04e7e7 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/vgatimer.sv @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// +// Joshua Potter +// 4/15/2015 +// +// Travels through each pixel in the VGA display, and properly emits horizontal +// and vertical pulses (as well as the active video) at approximately 25 MHz +// (given a 640x480 display). +// +////////////////////////////////////////////////////////////////////////////////// + +`include "display640x480.sv" + +module vgatimer( + input clk, + output hsync, vsync, activevideo, + output [`xbits-1:0] x, + output [`ybits-1:0] y + ); + + // These lines allow you to count every 2nd clock tick and 4th clock tick + // This is because, depending on the display mode, we may need to count at 50 MHz or 25 MHz. + reg [1:0] clk_count=0; + always_ff @(posedge clk) + clk_count <= clk_count + 2'b01; + + assign Every2ndTick = (clk_count[0] == 1'b1); + assign Every4thTick = (clk_count[1:0] == 2'b11); + + // This part instantiates an xy-counter using the appropriate clock tick counter + // xycounter #(`WholeLine, `WholeFrame) xy(clk, Every2ndTick, x, y); // Count at 50 MHz + xycounter #(`WholeLine, `WholeFrame) xy(clk, Every4thTick, x, y); // Count at 25 MHz + + // Generate the monitor sync signals + assign hsync = (x >= `hSyncStart && x <= `hSyncEnd) ? ~`hSyncPolarity : `hSyncPolarity; + assign vsync = (y >= `vSyncStart && y <= `vSyncEnd) ? ~`vSyncPolarity : `vSyncPolarity; + assign activevideo = (x < `hVisible && y < `vVisible); + +endmodule diff --git a/Project.srcs/sources_1/imports/src/xycounter.sv b/Project.srcs/sources_1/imports/src/xycounter.sv new file mode 100644 index 0000000..f7e2f80 --- /dev/null +++ b/Project.srcs/sources_1/imports/src/xycounter.sv @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/02/2015 02:32:38 PM +// Design Name: +// Module Name: xycounter +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module xycounter #(parameter width=2, height=2) ( + input clock, + input enable, + output reg [$clog2(width)-1:0] x = 0, + output reg [$clog2(height)-1:0] y = 0 + ); + + always_ff @(posedge clock) begin + if(enable) begin + if(x + 1 == width) begin + x <= 0; + y <= (y + 1 == height) ? 0 : y + 1; + end else begin + x <= x + 1; + end + end + end + +endmodule diff --git a/Project.xpr b/Project.xpr new file mode 100644 index 0000000..d28c848 --- /dev/null +++ b/Project.xpr @@ -0,0 +1,419 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/samples/Mars4_5.jar b/samples/Mars4_5.jar new file mode 100644 index 0000000..0021281 Binary files /dev/null and b/samples/Mars4_5.jar differ diff --git a/samples/guitar_hero/bmem_init.txt b/samples/guitar_hero/bmem_init.txt new file mode 100644 index 0000000..1283c7a --- /dev/null +++ b/samples/guitar_hero/bmem_init.txt @@ -0,0 +1,4352 @@ +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +ddd +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +ddd +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +ddd +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +ddd +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +ddd +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +ddd +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +ddd +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +ddd +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +eee +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff +fff \ No newline at end of file diff --git a/samples/guitar_hero/dmem_init.txt b/samples/guitar_hero/dmem_init.txt new file mode 100644 index 0000000..72cf8de --- /dev/null +++ b/samples/guitar_hero/dmem_init.txt @@ -0,0 +1 @@ +0 // data memory not used in this program \ No newline at end of file diff --git a/samples/guitar_hero/hero.asm b/samples/guitar_hero/hero.asm new file mode 100644 index 0000000..e84d0cc --- /dev/null +++ b/samples/guitar_hero/hero.asm @@ -0,0 +1,116 @@ +# Pong +# ================================== +# Author: Joshua Potter +# Date: 04/19/2015 + + +# Data Memory +# ---------------------------------- +# Note the board has a limited amount of space, so we try and make everything +# as compact as possible. +.data 0x2000 + + + +# Instruction Memory +# ---------------------------------- +# Be sure to set memory configuration Compact, Text at 0 +# Note data memory is offset at 0x2000, screen memory at 0x4000, and keyboard at 0x6000 +.text 0x0000 + add $0, $0, $0 # NOP + addi $sp, $0, 0x203c # top of the stack is the word at address [0x203c - 0x203f] +init: + addi $s0, $0, 1 # x velocity + addi $s1, $0, 40 # y velocity + addi $s2, $0, 580 # Ball Location + addi $s3, $0, 42 # Left Paddle Top Left + addi $s4, $0, 928 # Right Paddle Top Left + addi $s5, $0, 0xup # Up Button + addi $s6, $0, 0xdown # Down Button + addi $s7, $0, 0xspacebar # Spacebar +start: + lw $t0, 0x6000($0) # Check if spacebar pressed + bne $t0, $s7, main + addi $a0, $0, 1200 +main: # Main Game Loop + jal clear + jal update_ball + jal update_comp + jal update_player + jal draw + j main +end: + j end # No syscalls to exit + + +clear: # Reset up to $a0 screen locations to white + addi $sp, $sp, -4 + sw $a0, 0($sp) + addi $t0, $0, 4 +clear_loop: + addi $t1, $a0, 0x4000 # Screen memory begins at 0x4000 + addi $a0, $a0, -1 + sw $t0, 0($t1) + bne $a0, $0, reset_loop +clear_end: + lw $a0, 0($sp) + addi $sp, $sp, 4 + jr $ra + + +draw: # Draws the ball and paddles + addi $t0, $s3, 0 # Top left corners of each paddle + addi $t1, $s4, 0 + addi $t2, $0, 6 # Paddles are of height 7 characters +draw_paddles: + sw $0, 0($t0) # Black character code is 0 + sw $0, 0($t1) + addi $t0, $t0, 40 + addi $t1, $t1, 40 + addi $t2, $t2, -1 + bne $t2, $0, draw_paddles +draw_ball: + sw $s2, 0($t0) + jr $ra + + +update_ball: + add $s2, $s2, $s0 # Reposition's ball + add $s2, $s2, $s1 + jr $ra + + +update_comp: # Reposition's computer's paddle + jr $ra + + +update_player: # Repositions player's paddle + addi $a0, $0, 0 # Set so the paddle/ball doesn't move + lw $t0, 0x6000($0) + beq $t0, $s5, updatep_up + beq $t0, $s6, updatep_down +updatep_move: + add $s3, $s3, $a0 # Move player's paddle + jr $ra +updatep_up: + addi $a0, $0, -40 + j updatep_move +updatep_down: + addi $a0, $0, 40 + j updatep_move + + +pause: + addi $sp, $sp, -8 + sw $ra, 4($sp) + sw $a0, 0($sp) + sll $a0, $a0, 16 + beq $a0, $0, pse_done +pse_loop: + addi $a0, $a0, -1 + bne $a0, $0, pse_loop +pse_done: + lw $a0, 0($sp) + lw $ra, 4($sp) + addi $sp, $sp, 8 + jr $ra diff --git a/samples/guitar_hero/imem_init.txt b/samples/guitar_hero/imem_init.txt new file mode 100644 index 0000000..66e0368 --- /dev/null +++ b/samples/guitar_hero/imem_init.txt @@ -0,0 +1,13 @@ +00000020 +201d203c +20080003 +ac084000 +8c096000 +20010072 +10290001 +08000004 +20080001 +ac084000 +20080003 +ac084040 +0800000c diff --git a/samples/guitar_hero/regd_init.txt b/samples/guitar_hero/regd_init.txt new file mode 100644 index 0000000..463fdf1 --- /dev/null +++ b/samples/guitar_hero/regd_init.txt @@ -0,0 +1,32 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 \ No newline at end of file diff --git a/samples/guitar_hero/smem_init.txt b/samples/guitar_hero/smem_init.txt new file mode 100644 index 0000000..2e3b713 --- /dev/null +++ b/samples/guitar_hero/smem_init.txt @@ -0,0 +1,1200 @@ +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 +00000 \ No newline at end of file diff --git a/samples/pong/pong.asm b/samples/pong/pong.asm new file mode 100644 index 0000000..7e1856c --- /dev/null +++ b/samples/pong/pong.asm @@ -0,0 +1,193 @@ +# Pong +# ================================== +# Author: Joshua Potter +# Date: 04/19/2015 + + +# Data Memory +# ---------------------------------- +# Note the board has a limited amount of space, so we try and make everything +# as compact as possible. +.data 0x2000 + + +# Instruction Memory +# ---------------------------------- +# Be sure to set memory configuration Compact, Text at 0 +# Note data memory is offset at 0x2000, screen memory at 0x4000, and keyboard at 0x6000 +.text 0x0000 + add $0, $0, $0 # NOP + addi $sp, $0, 0x203c # top of the stack is the word at address [0x203c - 0x203f] +init: + addi $s0, $0, 1 # x velocity + addi $s1, $0, 40 # y velocity + addi $s2, $0, 620 # Ball Location + addi $s3, $0, 41 # Left Paddle Top Left + addi $s4, $0, 958 # Right Paddle Top Left + addi $s5, $0, 0x0075 # Up Button + addi $s6, $0, 0x0072 # Down Button + addi $s7, $0, 0x0029 # Spacebar + addi $t7, $0, 4 # Used to color the background +start: + lw $t0, 0x6000($0) # Check if spacebar pressed + bne $t0, $s7, start +main: # Main Game Loop + addi $a0, $0, 20 # Pause for a fifth of a second + jal pause + addi $a0, $0, 1200 # Clear 1200 screen locations + jal clear + jal update_ball + jal update_comp + jal update_player + jal draw + jal game_over # Check if should stop + bne $v0, $0, end + j main +end: + lw $t0, 0x6000($0) # Allow restarting + bne $t0, $s7, init + j end # No syscalls to exit + + +clear: # Reset up to $a0 screen locations to white + addi $sp, $sp, -4 + sw $a0, 0($sp) + add $t0, $0, $t7 +clear_loop: + addi $a0, $a0, -1 + addi $t1, $a0, 0x4000 # Screen memory begins at 0x4000 + sw $t0, 0($t1) + bne $a0, $0, clear_loop +clear_end: + lw $a0, 0($sp) + addi $sp, $sp, 4 + jr $ra + + +draw: # Draws the ball and paddles + addi $t0, $s3, 0 # Top left corners of each paddle + addi $t1, $s4, 0 + addi $t2, $0, 6 # Paddles are of height 7 characters +draw_paddles: + sw $0, 0x4000($t0) # Black character code is 0 + sw $0, 0x4000($t1) + addi $t0, $t0, 40 + addi $t1, $t1, 40 + addi $t2, $t2, -1 + bne $t2, $0, draw_paddles +draw_ball: + sw $0, 0x4000($s2) + jr $ra + + +update_ball: + add $t6, $s2, $s0 # Find future ball's position + add $t6, $t6, $s1 + addi $t0, $0, 7 + add $t1, $0, $s3 + add $t2, $0, $s4 +updx_ball: # Go through paddle positions and check + beq $t6, $t1, updx_reverse # for a collision + beq $t6, $t2, updx_reverse + addi $t1, $t1, 40 + addi $t2, $t2, 40 + addi $t0, $t0, -1 + bne $t0, $0, updx_ball + j updy_ball +updx_reverse: + sub $s0, $0, $s0 + slt $t0, $0, $s0 + beq $t0, $0, updx_1 + j updx_2 +updx_1: + addi $t7, $0, 1 + j updy_ball +updx_2: + addi $t7, $0, 2 +updy_ball: + slt $t0, $0, $t6 # Check if out top of screen + beq $t0, $0, updy_reverse + addi $t0, $0, 1200 # Check if out bottom of screen + slt $t0, $t0, $t6 + beq $t0, $0, upd_ball_done +updy_reverse: + sub $s1, $0, $s1 +upd_ball_done: + add $s2, $s2, $s0 + add $s2, $s2, $s1 + jr $ra + + +update_comp: # Reposition's computer's paddle + addi $a0, $0, 0 + slt $t0, $s2, $s4 + beq $t0, $0, updatec_down + j updatec_up +updatec_move: + add $s4, $s4, $a0 + jr $ra +updatec_up: + addi $t0, $0, 78 + beq $s4, $t0, updatec_move + addi $a0, $0, -40 + j updatec_move +updatec_down: + addi $t0, $0, 958 + beq $s4, $t0, updatec_move + addi $a0, $0, 40 + j updatec_move + + +update_player: # Repositions player's paddle + addi $a0, $0, 0 # Set so the paddle/ball doesn't move + lw $t0, 0x6000($0) + beq $t0, $s5, updatep_up + beq $t0, $s6, updatep_down +updatep_move: + add $s3, $s3, $a0 # Move player's paddle + jr $ra +updatep_up: + addi $t0, $0, 41 # Check if reached the top + beq $s3, $t0, updatep_move + addi $a0, $0, -40 + j updatep_move +updatep_down: + addi $t0, $0, 921 # Check if reached the bottom + beq $s3, $t0, updatep_move + addi $a0, $0, 40 + j updatep_move + + +game_over: + addi $v0, $0, 0 + addi $t0, $0, 29 + addi $t1, $0, 0 + addi $t2, $0, 39 +game_loop: + beq $s2, $t1, game_lost + beq $s2, $t2, game_lost + addi $t0, $t0, -1 + addi $t1, $t1, 40 + addi $t2, $t2, 40 + bne $t0, $0, game_loop + j game_on +game_lost: + addi $v0, $v0, 1 +game_on: + jr $ra + + +pause: + addi $sp, $sp, -8 + sw $ra, 4($sp) + sw $a0, 0($sp) + sll $a0, $a0, 16 + beq $a0, $0, pse_done +pse_loop: + addi $a0, $a0, -1 + bne $a0, $0, pse_loop +pse_done: + lw $a0, 0($sp) + lw $ra, 4($sp) + addi $sp, $sp, 8 + jr $ra